
module frv_issue_queue (
    input                       clk             ,
    input                       rst_n           ,
    input                       pd_rst          ,
    //ISQ Write Interface
    // Flush Interface
    input                       exp_flush       , // Exception Flush
    input [5:0]     exp_flush_tid   , // Exception Flush ID
    input                       bru_flush       , // Branch Prediction failed Flush
    // ==========================================================================
    // Issue Queue Interface
    output                      isq_ready       , // Issue Queue Ready , when issue queue is full , isq_ready will be pull up
    input                       isq_wreq        , // Issue Queue Request
    input [31:0]                isq_inst_data   ,
    input                       isq_exp_vld     ,
    input [4:0]                 isq_exp_code    ,
    input [31:0]                isq_pc_data     ,
    input [5:0]     isq_inst_id     , // Branch Prediction Flush ID
    //ALU Control Interface
    input                       isq_alu_vld     ,
    input                       isq_alu_land    ,
    input                       isq_alu_lor     ,
    input                       isq_alu_lxor    ,
    input                       isq_alu_sll     ,
    input                       isq_alu_srl     ,
    input                       isq_alu_sra     ,
    input                       isq_alu_add     ,
    input                       isq_alu_sub     ,
    input                       isq_alu_slt     ,
    input                       isq_alu_unsign  ,
    //Branch Control Interface
    input                       isq_bru_vld     ,
    input                       isq_bru_beq     ,
    input                       isq_bru_bne     ,
    input                       isq_bru_blt     ,
    input                       isq_bru_bge     ,
    input                       isq_bru_jal     ,
    input                       isq_bru_jalr    ,
    input [31:0]                isq_bp_taddr    , // bp target addr
    input                       isq_bp_taken    , // bp taken
    input [3:0]                 isq_bp_bhtv     , // BHT Entry Value
    input [31:0]                isq_bp_phtv     , // PHT Entry Value
    //LSU Control Interface
    input                       isq_lsu_vld     ,
    input                       isq_lsu_unsign  ,
    input                       isq_lsu_load    ,
    input                       isq_lsu_store   ,
    input                       isq_lsu_word    ,
    input                       isq_lsu_half    ,
    input                       isq_lsu_byte    ,
    //MDU Control Interface
    //TODO
    //CSR Control Interface
    input                       isq_csr_vld     ,
    input                       isq_csr_write   ,
    input                       isq_csr_set     ,
    input                       isq_csr_clr     , // CSR Clear
    //Operation number Interface
    input                       isq_rs1_vld     ,
    input                       isq_rs1_rdy     ,
    input[5:0]      isq_rs1_ind     ,
    input                       isq_rs1_type    ,
    input                       isq_rs2_vld     ,
    input                       isq_rs2_rdy     ,
    input[5:0]      isq_rs2_ind     ,
    input                       isq_rs2_type    ,
    input                       isq_imm_vld     ,
    input [31:0]                isq_imm_data    , // here we can compress the width
    input                       isq_rd_vld      ,
    // input [4:0]                 isq_rd_ind      ,
    // input [5:0]     isq_rdm_ind     ,
    input                       isq_pc_used     , // jal and auipc will use the pc value    
    // ==========================================================================
    //ALU Interface 
    output                      alu_req         ,
    output                      alu_ctrl_land   ,
    output                      alu_ctrl_lor    ,
    output                      alu_ctrl_lxor   ,
    output                      alu_ctrl_sll    ,
    output                      alu_ctrl_srl    ,
    output                      alu_ctrl_sra    ,
    output                      alu_ctrl_add    ,
    output                      alu_ctrl_sub    ,
    output                      alu_ctrl_slt    ,
    output                      alu_ctrl_unsign ,
    output [5:0]    alu_inst_id     , // Instruction ID                   
    // ALU operation 
    output [31:0]               alu_op1_val     ,
    output [31:0]               alu_op2_val     ,
    // output [5:0]                alu_rd_ind      ,
    // ALU fwd
    input                       alu_fwd_vld     ,
    input  [31:0]               alu_fwd_val     ,    
    input  [5:0]    alu_fwd_inst_id  ,    
    // ==========================================================================
    //BRU Interface
    output                      bru_req         ,
    output                      bru_ctrl_beq    ,
    output                      bru_ctrl_bne    ,
    output                      bru_ctrl_blt    ,
    output                      bru_ctrl_bge    ,
    output                      bru_ctrl_jal    ,
    output                      bru_ctrl_jalr   ,
    output [5:0]    bru_inst_id     , // Instruction ID  
    //BRU Operation Num
    output [31:0]               bru_pc_data     ,
    output [31:0]               bru_op1_val     ,
    output [31:0]               bru_op2_val     ,
    output [31:0]               bru_imm_val     ,
    // output [5:0]                bru_rd_ind      ,
    output                      bru_rd_vld      ,
    output [31:0]               bru_bp_taddr    , // bp target addr
    output                      bru_bp_taken    , // bp taken
    output [3:0]                bru_bp_bhtv     , // BHT Entry Value
    output [31:0]               bru_bp_phtv     , // PHT Entry Value  
    //BRU Foward Interface
    input                       bru_fwd_vld     ,
    input  [5:0]    bru_fwd_inst_id ,
    input                       bru_fwd_rd_vld  ,
    input  [31:0]               bru_fwd_val     ,          
    //LSU Interface                             
    input                       lsu_ready       ,
    output                      lsu_req         ,
    output                      lsu_ctrl_unsign ,
    output                      lsu_ctrl_load   ,
    output                      lsu_ctrl_store  ,
    output                      lsu_ctrl_word   ,
    output                      lsu_ctrl_half   ,
    output                      lsu_ctrl_byte   ,
    output [5:0]    lsu_inst_id     , // Instruction ID  
    //LSU Operation Number
    output [31:0]               lsu_op1_val     ,
    output [31:0]               lsu_op2_val     ,    
    output [31:0]               lsu_store_data  ,
    //LSU Foward Interface
    input  [5:0]    lsu_fwd_inst_id ,
    input                       lsu_fwd_vld     ,
    input                       lsu_fwd_rd_vld  ,
    input  [31:0]               lsu_fwd_val     , //rd value    
    input                       lsu_exp_vld     ,  //ignore it when exception feature is not implemented
    //Regfile Interface
    output [4:0]                rf_rs1_ind      ,
    input  [31:0]               rf_rs1_data     ,
    output [4:0]                rf_rs2_ind      ,
    input  [31:0]               rf_rs2_data     ,
    //ROB Interface
    output [5:0]    rob_rs1_ind     ,
    input  [31:0]               rob_rs1_data    ,
    output [5:0]    rob_rs2_ind     ,
    input  [31:0]               rob_rs2_data    
    //LSU Store Select Interface
);

wire                      isqe_wreq_0;
//wire                      isqe_flush_0;
wire                      isqe_valid_0;
wire                      isqe_ready_0;
wire                      alue_req_0;
wire                      alu_pick_vec_0;
wire                      alue_ctrl_land_0;
wire                      alue_ctrl_lor_0;
wire                      alue_ctrl_lxor_0;
wire                      alue_ctrl_sll_0;
wire                      alue_ctrl_srl_0;
wire                      alue_ctrl_sra_0;
wire                      alue_ctrl_add_0;
wire                      alue_ctrl_sub_0;
wire                      alue_ctrl_slt_0;
wire                      alue_ctrl_unsign_0;
wire [5:0]    alue_inst_id_0;
wire [31:0]               alue_op1_val_0;
wire [31:0]               alue_op2_val_0;
wire [5:0]                alue_rd_ind_0;
wire                      brue_req_0;
wire                      bru_pick_vec_0;
wire                      brue_ctrl_beq_0;
wire                      brue_ctrl_bne_0;
wire                      brue_ctrl_blt_0;
wire                      brue_ctrl_bge_0;
wire                      brue_ctrl_jal_0;
wire                      brue_ctrl_jalr_0;
wire [5:0]    brue_inst_id_0;
wire [31:0]               brue_pc_data_0;
wire [31:0]               brue_op1_val_0;
wire [31:0]               brue_op2_val_0;
wire [31:0]               brue_imm_val_0;
wire [5:0]                brue_rd_ind_0;
wire                      brue_rd_vld_0;
wire [31:0]               brue_bp_taddr_0;
wire                      brue_bp_taken_0;
wire [3:0]                brue_bp_bhtv_0;
wire [31:0]               brue_bp_phtv_0;
wire                      lsue_req_0;
wire                      lsu_pick_vec_0;
wire                      lsue_ctrl_unsign_0;
wire                      lsue_ctrl_load_0;
wire                      lsue_ctrl_store_0;
wire                      lsue_ctrl_word_0;
wire                      lsue_ctrl_half_0;
wire                      lsue_ctrl_byte_0;
wire [5:0]    lsue_inst_id_0;
wire [31:0]               lsue_op1_val_0;
wire [31:0]               lsue_op2_val_0;
wire [31:0]               lsue_store_data_0;
wire                      isqe_wreq_1;
//wire                      isqe_flush_1;
wire                      isqe_valid_1;
wire                      isqe_ready_1;
wire                      alue_req_1;
wire                      alu_pick_vec_1;
wire                      alue_ctrl_land_1;
wire                      alue_ctrl_lor_1;
wire                      alue_ctrl_lxor_1;
wire                      alue_ctrl_sll_1;
wire                      alue_ctrl_srl_1;
wire                      alue_ctrl_sra_1;
wire                      alue_ctrl_add_1;
wire                      alue_ctrl_sub_1;
wire                      alue_ctrl_slt_1;
wire                      alue_ctrl_unsign_1;
wire [5:0]    alue_inst_id_1;
wire [31:0]               alue_op1_val_1;
wire [31:0]               alue_op2_val_1;
wire [5:0]                alue_rd_ind_1;
wire                      brue_req_1;
wire                      bru_pick_vec_1;
wire                      brue_ctrl_beq_1;
wire                      brue_ctrl_bne_1;
wire                      brue_ctrl_blt_1;
wire                      brue_ctrl_bge_1;
wire                      brue_ctrl_jal_1;
wire                      brue_ctrl_jalr_1;
wire [5:0]    brue_inst_id_1;
wire [31:0]               brue_pc_data_1;
wire [31:0]               brue_op1_val_1;
wire [31:0]               brue_op2_val_1;
wire [31:0]               brue_imm_val_1;
wire [5:0]                brue_rd_ind_1;
wire                      brue_rd_vld_1;
wire [31:0]               brue_bp_taddr_1;
wire                      brue_bp_taken_1;
wire [3:0]                brue_bp_bhtv_1;
wire [31:0]               brue_bp_phtv_1;
wire                      lsue_req_1;
wire                      lsu_pick_vec_1;
wire                      lsue_ctrl_unsign_1;
wire                      lsue_ctrl_load_1;
wire                      lsue_ctrl_store_1;
wire                      lsue_ctrl_word_1;
wire                      lsue_ctrl_half_1;
wire                      lsue_ctrl_byte_1;
wire [5:0]    lsue_inst_id_1;
wire [31:0]               lsue_op1_val_1;
wire [31:0]               lsue_op2_val_1;
wire [31:0]               lsue_store_data_1;
wire                      isqe_wreq_2;
//wire                      isqe_flush_2;
wire                      isqe_valid_2;
wire                      isqe_ready_2;
wire                      alue_req_2;
wire                      alu_pick_vec_2;
wire                      alue_ctrl_land_2;
wire                      alue_ctrl_lor_2;
wire                      alue_ctrl_lxor_2;
wire                      alue_ctrl_sll_2;
wire                      alue_ctrl_srl_2;
wire                      alue_ctrl_sra_2;
wire                      alue_ctrl_add_2;
wire                      alue_ctrl_sub_2;
wire                      alue_ctrl_slt_2;
wire                      alue_ctrl_unsign_2;
wire [5:0]    alue_inst_id_2;
wire [31:0]               alue_op1_val_2;
wire [31:0]               alue_op2_val_2;
wire [5:0]                alue_rd_ind_2;
wire                      brue_req_2;
wire                      bru_pick_vec_2;
wire                      brue_ctrl_beq_2;
wire                      brue_ctrl_bne_2;
wire                      brue_ctrl_blt_2;
wire                      brue_ctrl_bge_2;
wire                      brue_ctrl_jal_2;
wire                      brue_ctrl_jalr_2;
wire [5:0]    brue_inst_id_2;
wire [31:0]               brue_pc_data_2;
wire [31:0]               brue_op1_val_2;
wire [31:0]               brue_op2_val_2;
wire [31:0]               brue_imm_val_2;
wire [5:0]                brue_rd_ind_2;
wire                      brue_rd_vld_2;
wire [31:0]               brue_bp_taddr_2;
wire                      brue_bp_taken_2;
wire [3:0]                brue_bp_bhtv_2;
wire [31:0]               brue_bp_phtv_2;
wire                      lsue_req_2;
wire                      lsu_pick_vec_2;
wire                      lsue_ctrl_unsign_2;
wire                      lsue_ctrl_load_2;
wire                      lsue_ctrl_store_2;
wire                      lsue_ctrl_word_2;
wire                      lsue_ctrl_half_2;
wire                      lsue_ctrl_byte_2;
wire [5:0]    lsue_inst_id_2;
wire [31:0]               lsue_op1_val_2;
wire [31:0]               lsue_op2_val_2;
wire [31:0]               lsue_store_data_2;
wire                      isqe_wreq_3;
//wire                      isqe_flush_3;
wire                      isqe_valid_3;
wire                      isqe_ready_3;
wire                      alue_req_3;
wire                      alu_pick_vec_3;
wire                      alue_ctrl_land_3;
wire                      alue_ctrl_lor_3;
wire                      alue_ctrl_lxor_3;
wire                      alue_ctrl_sll_3;
wire                      alue_ctrl_srl_3;
wire                      alue_ctrl_sra_3;
wire                      alue_ctrl_add_3;
wire                      alue_ctrl_sub_3;
wire                      alue_ctrl_slt_3;
wire                      alue_ctrl_unsign_3;
wire [5:0]    alue_inst_id_3;
wire [31:0]               alue_op1_val_3;
wire [31:0]               alue_op2_val_3;
wire [5:0]                alue_rd_ind_3;
wire                      brue_req_3;
wire                      bru_pick_vec_3;
wire                      brue_ctrl_beq_3;
wire                      brue_ctrl_bne_3;
wire                      brue_ctrl_blt_3;
wire                      brue_ctrl_bge_3;
wire                      brue_ctrl_jal_3;
wire                      brue_ctrl_jalr_3;
wire [5:0]    brue_inst_id_3;
wire [31:0]               brue_pc_data_3;
wire [31:0]               brue_op1_val_3;
wire [31:0]               brue_op2_val_3;
wire [31:0]               brue_imm_val_3;
wire [5:0]                brue_rd_ind_3;
wire                      brue_rd_vld_3;
wire [31:0]               brue_bp_taddr_3;
wire                      brue_bp_taken_3;
wire [3:0]                brue_bp_bhtv_3;
wire [31:0]               brue_bp_phtv_3;
wire                      lsue_req_3;
wire                      lsu_pick_vec_3;
wire                      lsue_ctrl_unsign_3;
wire                      lsue_ctrl_load_3;
wire                      lsue_ctrl_store_3;
wire                      lsue_ctrl_word_3;
wire                      lsue_ctrl_half_3;
wire                      lsue_ctrl_byte_3;
wire [5:0]    lsue_inst_id_3;
wire [31:0]               lsue_op1_val_3;
wire [31:0]               lsue_op2_val_3;
wire [31:0]               lsue_store_data_3;
wire                      isqe_wreq_4;
//wire                      isqe_flush_4;
wire                      isqe_valid_4;
wire                      isqe_ready_4;
wire                      alue_req_4;
wire                      alu_pick_vec_4;
wire                      alue_ctrl_land_4;
wire                      alue_ctrl_lor_4;
wire                      alue_ctrl_lxor_4;
wire                      alue_ctrl_sll_4;
wire                      alue_ctrl_srl_4;
wire                      alue_ctrl_sra_4;
wire                      alue_ctrl_add_4;
wire                      alue_ctrl_sub_4;
wire                      alue_ctrl_slt_4;
wire                      alue_ctrl_unsign_4;
wire [5:0]    alue_inst_id_4;
wire [31:0]               alue_op1_val_4;
wire [31:0]               alue_op2_val_4;
wire [5:0]                alue_rd_ind_4;
wire                      brue_req_4;
wire                      bru_pick_vec_4;
wire                      brue_ctrl_beq_4;
wire                      brue_ctrl_bne_4;
wire                      brue_ctrl_blt_4;
wire                      brue_ctrl_bge_4;
wire                      brue_ctrl_jal_4;
wire                      brue_ctrl_jalr_4;
wire [5:0]    brue_inst_id_4;
wire [31:0]               brue_pc_data_4;
wire [31:0]               brue_op1_val_4;
wire [31:0]               brue_op2_val_4;
wire [31:0]               brue_imm_val_4;
wire [5:0]                brue_rd_ind_4;
wire                      brue_rd_vld_4;
wire [31:0]               brue_bp_taddr_4;
wire                      brue_bp_taken_4;
wire [3:0]                brue_bp_bhtv_4;
wire [31:0]               brue_bp_phtv_4;
wire                      lsue_req_4;
wire                      lsu_pick_vec_4;
wire                      lsue_ctrl_unsign_4;
wire                      lsue_ctrl_load_4;
wire                      lsue_ctrl_store_4;
wire                      lsue_ctrl_word_4;
wire                      lsue_ctrl_half_4;
wire                      lsue_ctrl_byte_4;
wire [5:0]    lsue_inst_id_4;
wire [31:0]               lsue_op1_val_4;
wire [31:0]               lsue_op2_val_4;
wire [31:0]               lsue_store_data_4;
wire                      isqe_wreq_5;
//wire                      isqe_flush_5;
wire                      isqe_valid_5;
wire                      isqe_ready_5;
wire                      alue_req_5;
wire                      alu_pick_vec_5;
wire                      alue_ctrl_land_5;
wire                      alue_ctrl_lor_5;
wire                      alue_ctrl_lxor_5;
wire                      alue_ctrl_sll_5;
wire                      alue_ctrl_srl_5;
wire                      alue_ctrl_sra_5;
wire                      alue_ctrl_add_5;
wire                      alue_ctrl_sub_5;
wire                      alue_ctrl_slt_5;
wire                      alue_ctrl_unsign_5;
wire [5:0]    alue_inst_id_5;
wire [31:0]               alue_op1_val_5;
wire [31:0]               alue_op2_val_5;
wire [5:0]                alue_rd_ind_5;
wire                      brue_req_5;
wire                      bru_pick_vec_5;
wire                      brue_ctrl_beq_5;
wire                      brue_ctrl_bne_5;
wire                      brue_ctrl_blt_5;
wire                      brue_ctrl_bge_5;
wire                      brue_ctrl_jal_5;
wire                      brue_ctrl_jalr_5;
wire [5:0]    brue_inst_id_5;
wire [31:0]               brue_pc_data_5;
wire [31:0]               brue_op1_val_5;
wire [31:0]               brue_op2_val_5;
wire [31:0]               brue_imm_val_5;
wire [5:0]                brue_rd_ind_5;
wire                      brue_rd_vld_5;
wire [31:0]               brue_bp_taddr_5;
wire                      brue_bp_taken_5;
wire [3:0]                brue_bp_bhtv_5;
wire [31:0]               brue_bp_phtv_5;
wire                      lsue_req_5;
wire                      lsu_pick_vec_5;
wire                      lsue_ctrl_unsign_5;
wire                      lsue_ctrl_load_5;
wire                      lsue_ctrl_store_5;
wire                      lsue_ctrl_word_5;
wire                      lsue_ctrl_half_5;
wire                      lsue_ctrl_byte_5;
wire [5:0]    lsue_inst_id_5;
wire [31:0]               lsue_op1_val_5;
wire [31:0]               lsue_op2_val_5;
wire [31:0]               lsue_store_data_5;
wire                      isqe_wreq_6;
//wire                      isqe_flush_6;
wire                      isqe_valid_6;
wire                      isqe_ready_6;
wire                      alue_req_6;
wire                      alu_pick_vec_6;
wire                      alue_ctrl_land_6;
wire                      alue_ctrl_lor_6;
wire                      alue_ctrl_lxor_6;
wire                      alue_ctrl_sll_6;
wire                      alue_ctrl_srl_6;
wire                      alue_ctrl_sra_6;
wire                      alue_ctrl_add_6;
wire                      alue_ctrl_sub_6;
wire                      alue_ctrl_slt_6;
wire                      alue_ctrl_unsign_6;
wire [5:0]    alue_inst_id_6;
wire [31:0]               alue_op1_val_6;
wire [31:0]               alue_op2_val_6;
wire [5:0]                alue_rd_ind_6;
wire                      brue_req_6;
wire                      bru_pick_vec_6;
wire                      brue_ctrl_beq_6;
wire                      brue_ctrl_bne_6;
wire                      brue_ctrl_blt_6;
wire                      brue_ctrl_bge_6;
wire                      brue_ctrl_jal_6;
wire                      brue_ctrl_jalr_6;
wire [5:0]    brue_inst_id_6;
wire [31:0]               brue_pc_data_6;
wire [31:0]               brue_op1_val_6;
wire [31:0]               brue_op2_val_6;
wire [31:0]               brue_imm_val_6;
wire [5:0]                brue_rd_ind_6;
wire                      brue_rd_vld_6;
wire [31:0]               brue_bp_taddr_6;
wire                      brue_bp_taken_6;
wire [3:0]                brue_bp_bhtv_6;
wire [31:0]               brue_bp_phtv_6;
wire                      lsue_req_6;
wire                      lsu_pick_vec_6;
wire                      lsue_ctrl_unsign_6;
wire                      lsue_ctrl_load_6;
wire                      lsue_ctrl_store_6;
wire                      lsue_ctrl_word_6;
wire                      lsue_ctrl_half_6;
wire                      lsue_ctrl_byte_6;
wire [5:0]    lsue_inst_id_6;
wire [31:0]               lsue_op1_val_6;
wire [31:0]               lsue_op2_val_6;
wire [31:0]               lsue_store_data_6;
wire                      isqe_wreq_7;
//wire                      isqe_flush_7;
wire                      isqe_valid_7;
wire                      isqe_ready_7;
wire                      alue_req_7;
wire                      alu_pick_vec_7;
wire                      alue_ctrl_land_7;
wire                      alue_ctrl_lor_7;
wire                      alue_ctrl_lxor_7;
wire                      alue_ctrl_sll_7;
wire                      alue_ctrl_srl_7;
wire                      alue_ctrl_sra_7;
wire                      alue_ctrl_add_7;
wire                      alue_ctrl_sub_7;
wire                      alue_ctrl_slt_7;
wire                      alue_ctrl_unsign_7;
wire [5:0]    alue_inst_id_7;
wire [31:0]               alue_op1_val_7;
wire [31:0]               alue_op2_val_7;
wire [5:0]                alue_rd_ind_7;
wire                      brue_req_7;
wire                      bru_pick_vec_7;
wire                      brue_ctrl_beq_7;
wire                      brue_ctrl_bne_7;
wire                      brue_ctrl_blt_7;
wire                      brue_ctrl_bge_7;
wire                      brue_ctrl_jal_7;
wire                      brue_ctrl_jalr_7;
wire [5:0]    brue_inst_id_7;
wire [31:0]               brue_pc_data_7;
wire [31:0]               brue_op1_val_7;
wire [31:0]               brue_op2_val_7;
wire [31:0]               brue_imm_val_7;
wire [5:0]                brue_rd_ind_7;
wire                      brue_rd_vld_7;
wire [31:0]               brue_bp_taddr_7;
wire                      brue_bp_taken_7;
wire [3:0]                brue_bp_bhtv_7;
wire [31:0]               brue_bp_phtv_7;
wire                      lsue_req_7;
wire                      lsu_pick_vec_7;
wire                      lsue_ctrl_unsign_7;
wire                      lsue_ctrl_load_7;
wire                      lsue_ctrl_store_7;
wire                      lsue_ctrl_word_7;
wire                      lsue_ctrl_half_7;
wire                      lsue_ctrl_byte_7;
wire [5:0]    lsue_inst_id_7;
wire [31:0]               lsue_op1_val_7;
wire [31:0]               lsue_op2_val_7;
wire [31:0]               lsue_store_data_7;
wire                      isqe_wreq_8;
//wire                      isqe_flush_8;
wire                      isqe_valid_8;
wire                      isqe_ready_8;
wire                      alue_req_8;
wire                      alu_pick_vec_8;
wire                      alue_ctrl_land_8;
wire                      alue_ctrl_lor_8;
wire                      alue_ctrl_lxor_8;
wire                      alue_ctrl_sll_8;
wire                      alue_ctrl_srl_8;
wire                      alue_ctrl_sra_8;
wire                      alue_ctrl_add_8;
wire                      alue_ctrl_sub_8;
wire                      alue_ctrl_slt_8;
wire                      alue_ctrl_unsign_8;
wire [5:0]    alue_inst_id_8;
wire [31:0]               alue_op1_val_8;
wire [31:0]               alue_op2_val_8;
wire [5:0]                alue_rd_ind_8;
wire                      brue_req_8;
wire                      bru_pick_vec_8;
wire                      brue_ctrl_beq_8;
wire                      brue_ctrl_bne_8;
wire                      brue_ctrl_blt_8;
wire                      brue_ctrl_bge_8;
wire                      brue_ctrl_jal_8;
wire                      brue_ctrl_jalr_8;
wire [5:0]    brue_inst_id_8;
wire [31:0]               brue_pc_data_8;
wire [31:0]               brue_op1_val_8;
wire [31:0]               brue_op2_val_8;
wire [31:0]               brue_imm_val_8;
wire [5:0]                brue_rd_ind_8;
wire                      brue_rd_vld_8;
wire [31:0]               brue_bp_taddr_8;
wire                      brue_bp_taken_8;
wire [3:0]                brue_bp_bhtv_8;
wire [31:0]               brue_bp_phtv_8;
wire                      lsue_req_8;
wire                      lsu_pick_vec_8;
wire                      lsue_ctrl_unsign_8;
wire                      lsue_ctrl_load_8;
wire                      lsue_ctrl_store_8;
wire                      lsue_ctrl_word_8;
wire                      lsue_ctrl_half_8;
wire                      lsue_ctrl_byte_8;
wire [5:0]    lsue_inst_id_8;
wire [31:0]               lsue_op1_val_8;
wire [31:0]               lsue_op2_val_8;
wire [31:0]               lsue_store_data_8;
wire                      isqe_wreq_9;
//wire                      isqe_flush_9;
wire                      isqe_valid_9;
wire                      isqe_ready_9;
wire                      alue_req_9;
wire                      alu_pick_vec_9;
wire                      alue_ctrl_land_9;
wire                      alue_ctrl_lor_9;
wire                      alue_ctrl_lxor_9;
wire                      alue_ctrl_sll_9;
wire                      alue_ctrl_srl_9;
wire                      alue_ctrl_sra_9;
wire                      alue_ctrl_add_9;
wire                      alue_ctrl_sub_9;
wire                      alue_ctrl_slt_9;
wire                      alue_ctrl_unsign_9;
wire [5:0]    alue_inst_id_9;
wire [31:0]               alue_op1_val_9;
wire [31:0]               alue_op2_val_9;
wire [5:0]                alue_rd_ind_9;
wire                      brue_req_9;
wire                      bru_pick_vec_9;
wire                      brue_ctrl_beq_9;
wire                      brue_ctrl_bne_9;
wire                      brue_ctrl_blt_9;
wire                      brue_ctrl_bge_9;
wire                      brue_ctrl_jal_9;
wire                      brue_ctrl_jalr_9;
wire [5:0]    brue_inst_id_9;
wire [31:0]               brue_pc_data_9;
wire [31:0]               brue_op1_val_9;
wire [31:0]               brue_op2_val_9;
wire [31:0]               brue_imm_val_9;
wire [5:0]                brue_rd_ind_9;
wire                      brue_rd_vld_9;
wire [31:0]               brue_bp_taddr_9;
wire                      brue_bp_taken_9;
wire [3:0]                brue_bp_bhtv_9;
wire [31:0]               brue_bp_phtv_9;
wire                      lsue_req_9;
wire                      lsu_pick_vec_9;
wire                      lsue_ctrl_unsign_9;
wire                      lsue_ctrl_load_9;
wire                      lsue_ctrl_store_9;
wire                      lsue_ctrl_word_9;
wire                      lsue_ctrl_half_9;
wire                      lsue_ctrl_byte_9;
wire [5:0]    lsue_inst_id_9;
wire [31:0]               lsue_op1_val_9;
wire [31:0]               lsue_op2_val_9;
wire [31:0]               lsue_store_data_9;
wire                      isqe_wreq_10;
//wire                      isqe_flush_10;
wire                      isqe_valid_10;
wire                      isqe_ready_10;
wire                      alue_req_10;
wire                      alu_pick_vec_10;
wire                      alue_ctrl_land_10;
wire                      alue_ctrl_lor_10;
wire                      alue_ctrl_lxor_10;
wire                      alue_ctrl_sll_10;
wire                      alue_ctrl_srl_10;
wire                      alue_ctrl_sra_10;
wire                      alue_ctrl_add_10;
wire                      alue_ctrl_sub_10;
wire                      alue_ctrl_slt_10;
wire                      alue_ctrl_unsign_10;
wire [5:0]    alue_inst_id_10;
wire [31:0]               alue_op1_val_10;
wire [31:0]               alue_op2_val_10;
wire [5:0]                alue_rd_ind_10;
wire                      brue_req_10;
wire                      bru_pick_vec_10;
wire                      brue_ctrl_beq_10;
wire                      brue_ctrl_bne_10;
wire                      brue_ctrl_blt_10;
wire                      brue_ctrl_bge_10;
wire                      brue_ctrl_jal_10;
wire                      brue_ctrl_jalr_10;
wire [5:0]    brue_inst_id_10;
wire [31:0]               brue_pc_data_10;
wire [31:0]               brue_op1_val_10;
wire [31:0]               brue_op2_val_10;
wire [31:0]               brue_imm_val_10;
wire [5:0]                brue_rd_ind_10;
wire                      brue_rd_vld_10;
wire [31:0]               brue_bp_taddr_10;
wire                      brue_bp_taken_10;
wire [3:0]                brue_bp_bhtv_10;
wire [31:0]               brue_bp_phtv_10;
wire                      lsue_req_10;
wire                      lsu_pick_vec_10;
wire                      lsue_ctrl_unsign_10;
wire                      lsue_ctrl_load_10;
wire                      lsue_ctrl_store_10;
wire                      lsue_ctrl_word_10;
wire                      lsue_ctrl_half_10;
wire                      lsue_ctrl_byte_10;
wire [5:0]    lsue_inst_id_10;
wire [31:0]               lsue_op1_val_10;
wire [31:0]               lsue_op2_val_10;
wire [31:0]               lsue_store_data_10;
wire                      isqe_wreq_11;
//wire                      isqe_flush_11;
wire                      isqe_valid_11;
wire                      isqe_ready_11;
wire                      alue_req_11;
wire                      alu_pick_vec_11;
wire                      alue_ctrl_land_11;
wire                      alue_ctrl_lor_11;
wire                      alue_ctrl_lxor_11;
wire                      alue_ctrl_sll_11;
wire                      alue_ctrl_srl_11;
wire                      alue_ctrl_sra_11;
wire                      alue_ctrl_add_11;
wire                      alue_ctrl_sub_11;
wire                      alue_ctrl_slt_11;
wire                      alue_ctrl_unsign_11;
wire [5:0]    alue_inst_id_11;
wire [31:0]               alue_op1_val_11;
wire [31:0]               alue_op2_val_11;
wire [5:0]                alue_rd_ind_11;
wire                      brue_req_11;
wire                      bru_pick_vec_11;
wire                      brue_ctrl_beq_11;
wire                      brue_ctrl_bne_11;
wire                      brue_ctrl_blt_11;
wire                      brue_ctrl_bge_11;
wire                      brue_ctrl_jal_11;
wire                      brue_ctrl_jalr_11;
wire [5:0]    brue_inst_id_11;
wire [31:0]               brue_pc_data_11;
wire [31:0]               brue_op1_val_11;
wire [31:0]               brue_op2_val_11;
wire [31:0]               brue_imm_val_11;
wire [5:0]                brue_rd_ind_11;
wire                      brue_rd_vld_11;
wire [31:0]               brue_bp_taddr_11;
wire                      brue_bp_taken_11;
wire [3:0]                brue_bp_bhtv_11;
wire [31:0]               brue_bp_phtv_11;
wire                      lsue_req_11;
wire                      lsu_pick_vec_11;
wire                      lsue_ctrl_unsign_11;
wire                      lsue_ctrl_load_11;
wire                      lsue_ctrl_store_11;
wire                      lsue_ctrl_word_11;
wire                      lsue_ctrl_half_11;
wire                      lsue_ctrl_byte_11;
wire [5:0]    lsue_inst_id_11;
wire [31:0]               lsue_op1_val_11;
wire [31:0]               lsue_op2_val_11;
wire [31:0]               lsue_store_data_11;
wire                      isqe_wreq_12;
//wire                      isqe_flush_12;
wire                      isqe_valid_12;
wire                      isqe_ready_12;
wire                      alue_req_12;
wire                      alu_pick_vec_12;
wire                      alue_ctrl_land_12;
wire                      alue_ctrl_lor_12;
wire                      alue_ctrl_lxor_12;
wire                      alue_ctrl_sll_12;
wire                      alue_ctrl_srl_12;
wire                      alue_ctrl_sra_12;
wire                      alue_ctrl_add_12;
wire                      alue_ctrl_sub_12;
wire                      alue_ctrl_slt_12;
wire                      alue_ctrl_unsign_12;
wire [5:0]    alue_inst_id_12;
wire [31:0]               alue_op1_val_12;
wire [31:0]               alue_op2_val_12;
wire [5:0]                alue_rd_ind_12;
wire                      brue_req_12;
wire                      bru_pick_vec_12;
wire                      brue_ctrl_beq_12;
wire                      brue_ctrl_bne_12;
wire                      brue_ctrl_blt_12;
wire                      brue_ctrl_bge_12;
wire                      brue_ctrl_jal_12;
wire                      brue_ctrl_jalr_12;
wire [5:0]    brue_inst_id_12;
wire [31:0]               brue_pc_data_12;
wire [31:0]               brue_op1_val_12;
wire [31:0]               brue_op2_val_12;
wire [31:0]               brue_imm_val_12;
wire [5:0]                brue_rd_ind_12;
wire                      brue_rd_vld_12;
wire [31:0]               brue_bp_taddr_12;
wire                      brue_bp_taken_12;
wire [3:0]                brue_bp_bhtv_12;
wire [31:0]               brue_bp_phtv_12;
wire                      lsue_req_12;
wire                      lsu_pick_vec_12;
wire                      lsue_ctrl_unsign_12;
wire                      lsue_ctrl_load_12;
wire                      lsue_ctrl_store_12;
wire                      lsue_ctrl_word_12;
wire                      lsue_ctrl_half_12;
wire                      lsue_ctrl_byte_12;
wire [5:0]    lsue_inst_id_12;
wire [31:0]               lsue_op1_val_12;
wire [31:0]               lsue_op2_val_12;
wire [31:0]               lsue_store_data_12;
wire                      isqe_wreq_13;
//wire                      isqe_flush_13;
wire                      isqe_valid_13;
wire                      isqe_ready_13;
wire                      alue_req_13;
wire                      alu_pick_vec_13;
wire                      alue_ctrl_land_13;
wire                      alue_ctrl_lor_13;
wire                      alue_ctrl_lxor_13;
wire                      alue_ctrl_sll_13;
wire                      alue_ctrl_srl_13;
wire                      alue_ctrl_sra_13;
wire                      alue_ctrl_add_13;
wire                      alue_ctrl_sub_13;
wire                      alue_ctrl_slt_13;
wire                      alue_ctrl_unsign_13;
wire [5:0]    alue_inst_id_13;
wire [31:0]               alue_op1_val_13;
wire [31:0]               alue_op2_val_13;
wire [5:0]                alue_rd_ind_13;
wire                      brue_req_13;
wire                      bru_pick_vec_13;
wire                      brue_ctrl_beq_13;
wire                      brue_ctrl_bne_13;
wire                      brue_ctrl_blt_13;
wire                      brue_ctrl_bge_13;
wire                      brue_ctrl_jal_13;
wire                      brue_ctrl_jalr_13;
wire [5:0]    brue_inst_id_13;
wire [31:0]               brue_pc_data_13;
wire [31:0]               brue_op1_val_13;
wire [31:0]               brue_op2_val_13;
wire [31:0]               brue_imm_val_13;
wire [5:0]                brue_rd_ind_13;
wire                      brue_rd_vld_13;
wire [31:0]               brue_bp_taddr_13;
wire                      brue_bp_taken_13;
wire [3:0]                brue_bp_bhtv_13;
wire [31:0]               brue_bp_phtv_13;
wire                      lsue_req_13;
wire                      lsu_pick_vec_13;
wire                      lsue_ctrl_unsign_13;
wire                      lsue_ctrl_load_13;
wire                      lsue_ctrl_store_13;
wire                      lsue_ctrl_word_13;
wire                      lsue_ctrl_half_13;
wire                      lsue_ctrl_byte_13;
wire [5:0]    lsue_inst_id_13;
wire [31:0]               lsue_op1_val_13;
wire [31:0]               lsue_op2_val_13;
wire [31:0]               lsue_store_data_13;
wire                      isqe_wreq_14;
//wire                      isqe_flush_14;
wire                      isqe_valid_14;
wire                      isqe_ready_14;
wire                      alue_req_14;
wire                      alu_pick_vec_14;
wire                      alue_ctrl_land_14;
wire                      alue_ctrl_lor_14;
wire                      alue_ctrl_lxor_14;
wire                      alue_ctrl_sll_14;
wire                      alue_ctrl_srl_14;
wire                      alue_ctrl_sra_14;
wire                      alue_ctrl_add_14;
wire                      alue_ctrl_sub_14;
wire                      alue_ctrl_slt_14;
wire                      alue_ctrl_unsign_14;
wire [5:0]    alue_inst_id_14;
wire [31:0]               alue_op1_val_14;
wire [31:0]               alue_op2_val_14;
wire [5:0]                alue_rd_ind_14;
wire                      brue_req_14;
wire                      bru_pick_vec_14;
wire                      brue_ctrl_beq_14;
wire                      brue_ctrl_bne_14;
wire                      brue_ctrl_blt_14;
wire                      brue_ctrl_bge_14;
wire                      brue_ctrl_jal_14;
wire                      brue_ctrl_jalr_14;
wire [5:0]    brue_inst_id_14;
wire [31:0]               brue_pc_data_14;
wire [31:0]               brue_op1_val_14;
wire [31:0]               brue_op2_val_14;
wire [31:0]               brue_imm_val_14;
wire [5:0]                brue_rd_ind_14;
wire                      brue_rd_vld_14;
wire [31:0]               brue_bp_taddr_14;
wire                      brue_bp_taken_14;
wire [3:0]                brue_bp_bhtv_14;
wire [31:0]               brue_bp_phtv_14;
wire                      lsue_req_14;
wire                      lsu_pick_vec_14;
wire                      lsue_ctrl_unsign_14;
wire                      lsue_ctrl_load_14;
wire                      lsue_ctrl_store_14;
wire                      lsue_ctrl_word_14;
wire                      lsue_ctrl_half_14;
wire                      lsue_ctrl_byte_14;
wire [5:0]    lsue_inst_id_14;
wire [31:0]               lsue_op1_val_14;
wire [31:0]               lsue_op2_val_14;
wire [31:0]               lsue_store_data_14;
wire                      isqe_wreq_15;
//wire                      isqe_flush_15;
wire                      isqe_valid_15;
wire                      isqe_ready_15;
wire                      alue_req_15;
wire                      alu_pick_vec_15;
wire                      alue_ctrl_land_15;
wire                      alue_ctrl_lor_15;
wire                      alue_ctrl_lxor_15;
wire                      alue_ctrl_sll_15;
wire                      alue_ctrl_srl_15;
wire                      alue_ctrl_sra_15;
wire                      alue_ctrl_add_15;
wire                      alue_ctrl_sub_15;
wire                      alue_ctrl_slt_15;
wire                      alue_ctrl_unsign_15;
wire [5:0]    alue_inst_id_15;
wire [31:0]               alue_op1_val_15;
wire [31:0]               alue_op2_val_15;
wire [5:0]                alue_rd_ind_15;
wire                      brue_req_15;
wire                      bru_pick_vec_15;
wire                      brue_ctrl_beq_15;
wire                      brue_ctrl_bne_15;
wire                      brue_ctrl_blt_15;
wire                      brue_ctrl_bge_15;
wire                      brue_ctrl_jal_15;
wire                      brue_ctrl_jalr_15;
wire [5:0]    brue_inst_id_15;
wire [31:0]               brue_pc_data_15;
wire [31:0]               brue_op1_val_15;
wire [31:0]               brue_op2_val_15;
wire [31:0]               brue_imm_val_15;
wire [5:0]                brue_rd_ind_15;
wire                      brue_rd_vld_15;
wire [31:0]               brue_bp_taddr_15;
wire                      brue_bp_taken_15;
wire [3:0]                brue_bp_bhtv_15;
wire [31:0]               brue_bp_phtv_15;
wire                      lsue_req_15;
wire                      lsu_pick_vec_15;
wire                      lsue_ctrl_unsign_15;
wire                      lsue_ctrl_load_15;
wire                      lsue_ctrl_store_15;
wire                      lsue_ctrl_word_15;
wire                      lsue_ctrl_half_15;
wire                      lsue_ctrl_byte_15;
wire [5:0]    lsue_inst_id_15;
wire [31:0]               lsue_op1_val_15;
wire [31:0]               lsue_op2_val_15;
wire [31:0]               lsue_store_data_15;

wire [16-1:0]            isq_idle_vec;
wire [16-1:0]            isq_idle_pick;
wire                                 isq_almost_full;
wire                                 isq_full;
wire [4:0]             entry_num,entry_num_nxt;
wire                                 isq_ready_nxt;

wire                                 reg_rs1_rdy;
wire [31:0]                          reg_rs1_val;
wire                                 reg_rs2_rdy;
wire [31:0]                          reg_rs2_val;
wire [31:0]                          rs1_fwd_val;
wire [31:0]                          rs2_fwd_val;

//ALU Pick Port
wire                                 alu_req_nxt         ;
wire                                 alu_ctrl_land_nxt   ;
wire                                 alu_ctrl_lor_nxt    ;
wire                                 alu_ctrl_lxor_nxt   ;
wire                                 alu_ctrl_sll_nxt    ;
wire                                 alu_ctrl_srl_nxt    ;
wire                                 alu_ctrl_sra_nxt    ;
wire                                 alu_ctrl_add_nxt    ;
wire                                 alu_ctrl_sub_nxt    ;
wire                                 alu_ctrl_slt_nxt    ;
wire                                 alu_ctrl_unsign_nxt ;
wire [5:0]               alu_inst_id_nxt     ; 
wire [31:0]                          alu_op1_val_nxt     ;
wire [31:0]                          alu_op2_val_nxt     ;
wire [4-1:0]           alu_pick_index      ;
wire [5:0]               alu_pick_inst_id    ;
wire              alu_sel_0;
wire              alu_sel_1;
wire              alu_sel_2;
wire              alu_sel_3;
wire              alu_sel_4;
wire              alu_sel_5;
wire              alu_sel_6;
wire              alu_sel_7;
wire              alu_sel_8;
wire              alu_sel_9;
wire              alu_sel_10;
wire              alu_sel_11;
wire              alu_sel_12;
wire              alu_sel_13;
wire              alu_sel_14;
wire              alu_sel_15;

//BRU Pick Port
wire                                 bru_req_nxt         ;
wire                                 bru_ctrl_beq_nxt    ;
wire                                 bru_ctrl_bne_nxt    ;
wire                                 bru_ctrl_blt_nxt    ;
wire                                 bru_ctrl_bge_nxt    ;
wire                                 bru_ctrl_jal_nxt    ;
wire                                 bru_ctrl_jalr_nxt   ;
wire [5:0]               bru_inst_id_nxt     ; // Instruction ID  
wire [31:0]                          bru_pc_data_nxt     ;
wire [31:0]                          bru_op1_val_nxt     ;
wire [31:0]                          bru_op2_val_nxt     ;
wire [31:0]                          bru_imm_val_nxt     ;
// wire [5:0]                           bru_rd_ind_nxt      ;
wire                                 bru_rd_vld_nxt      ;
// This function waste too much space, it must be delete when we update the Branch Predictor
wire [31:0]                          bru_bp_taddr_nxt    ; // bp target addr
wire                                 bru_bp_taken_nxt    ; // bp taken
wire [3:0]                           bru_bp_bhtv_nxt     ; // BHT Entry Value
wire [31:0]                          bru_bp_phtv_nxt     ; // PHT Entry Value  
wire [4-1:0]           bru_pick_index      ;
wire [5:0]               bru_pick_inst_id    ;

wire              bru_sel_0;
wire              bru_sel_1;
wire              bru_sel_2;
wire              bru_sel_3;
wire              bru_sel_4;
wire              bru_sel_5;
wire              bru_sel_6;
wire              bru_sel_7;
wire              bru_sel_8;
wire              bru_sel_9;
wire              bru_sel_10;
wire              bru_sel_11;
wire              bru_sel_12;
wire              bru_sel_13;
wire              bru_sel_14;
wire              bru_sel_15;
//LSU Pick Port
wire                                 lsu_req_nxt         ;
wire                                 lsu_ctrl_unsign_nxt ;
wire                                 lsu_ctrl_load_nxt   ;
wire                                 lsu_ctrl_store_nxt  ;
wire                                 lsu_ctrl_word_nxt   ;
wire                                 lsu_ctrl_half_nxt   ;
wire                                 lsu_ctrl_byte_nxt   ;
wire [5:0]               lsu_inst_id_nxt     ; // Instruction ID  
wire [31:0]                          lsu_op1_val_nxt     ;
wire [31:0]                          lsu_op2_val_nxt     ;    
wire [31:0]                          lsu_store_data_nxt  ;
wire [4-1:0]           lsu_pick_index      ;
wire [5:0]               lsu_pick_inst_id    ;
// `psv_begin
// for i in range(0,16):
//     print("wire                     lsu_pick_vec_%d;"%i);
// `psv_end

wire                      sob_wreq         ;
wire[5:0]     sob_inst_id      ;   
wire                      sob_flush        ;
wire[5:0]     sob_flush_id     ;
wire[5:0]     sob_head_inst_id ;
wire                      sob_head_vld     ;
wire                      sob_rreq         ;
wire                      sob_rdy          ;

wire              lsu_sel_0;
wire              lsu_sel_1;
wire              lsu_sel_2;
wire              lsu_sel_3;
wire              lsu_sel_4;
wire              lsu_sel_5;
wire              lsu_sel_6;
wire              lsu_sel_7;
wire              lsu_sel_8;
wire              lsu_sel_9;
wire              lsu_sel_10;
wire              lsu_sel_11;
wire              lsu_sel_12;
wire              lsu_sel_13;
wire              lsu_sel_14;
wire              lsu_sel_15;

//Pick an idle ISQ Entry to save Instrucion OP
assign isq_idle_vec[0] = ~isqe_valid_0;
assign isq_idle_vec[1] = ~isqe_valid_1;
assign isq_idle_vec[2] = ~isqe_valid_2;
assign isq_idle_vec[3] = ~isqe_valid_3;
assign isq_idle_vec[4] = ~isqe_valid_4;
assign isq_idle_vec[5] = ~isqe_valid_5;
assign isq_idle_vec[6] = ~isqe_valid_6;
assign isq_idle_vec[7] = ~isqe_valid_7;
assign isq_idle_vec[8] = ~isqe_valid_8;
assign isq_idle_vec[9] = ~isqe_valid_9;
assign isq_idle_vec[10] = ~isqe_valid_10;
assign isq_idle_vec[11] = ~isqe_valid_11;
assign isq_idle_vec[12] = ~isqe_valid_12;
assign isq_idle_vec[13] = ~isqe_valid_13;
assign isq_idle_vec[14] = ~isqe_valid_14;
assign isq_idle_vec[15] = ~isqe_valid_15;

isq_idle_pick_dec _isq_idle_pick_dec(isq_idle_vec,isq_idle_pick);

assign isqe_wreq_0 = isq_idle_pick[0] && isq_wreq && ~isq_full;
assign isqe_wreq_1 = isq_idle_pick[1] && isq_wreq && ~isq_full;
assign isqe_wreq_2 = isq_idle_pick[2] && isq_wreq && ~isq_full;
assign isqe_wreq_3 = isq_idle_pick[3] && isq_wreq && ~isq_full;
assign isqe_wreq_4 = isq_idle_pick[4] && isq_wreq && ~isq_full;
assign isqe_wreq_5 = isq_idle_pick[5] && isq_wreq && ~isq_full;
assign isqe_wreq_6 = isq_idle_pick[6] && isq_wreq && ~isq_full;
assign isqe_wreq_7 = isq_idle_pick[7] && isq_wreq && ~isq_full;
assign isqe_wreq_8 = isq_idle_pick[8] && isq_wreq && ~isq_full;
assign isqe_wreq_9 = isq_idle_pick[9] && isq_wreq && ~isq_full;
assign isqe_wreq_10 = isq_idle_pick[10] && isq_wreq && ~isq_full;
assign isqe_wreq_11 = isq_idle_pick[11] && isq_wreq && ~isq_full;
assign isqe_wreq_12 = isq_idle_pick[12] && isq_wreq && ~isq_full;
assign isqe_wreq_13 = isq_idle_pick[13] && isq_wreq && ~isq_full;
assign isqe_wreq_14 = isq_idle_pick[14] && isq_wreq && ~isq_full;
assign isqe_wreq_15 = isq_idle_pick[15] && isq_wreq && ~isq_full;

wire [5:0] rs1_index_map;
wire [5:0] rs2_index_map;

assign rs1_index_map = isq_rs1_ind;
assign rs2_index_map = isq_rs2_ind;

wire rs1_alu_match;
wire rs1_bru_match;
wire rs1_lsu_match;

wire rs2_alu_match;
wire rs2_bru_match;
wire rs2_lsu_match;

assign rs1_alu_match = isq_rs1_type && rs1_index_map == alu_fwd_inst_id && alu_fwd_vld;
assign rs1_bru_match = isq_rs1_type && rs1_index_map == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld;
assign rs1_lsu_match = isq_rs1_type && rs1_index_map == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld;

//FU Foward DataPath
assign rs1_fu_match = rs1_alu_match || rs1_bru_match || rs1_lsu_match;

assign rs1_fwd_val = ({32{rs1_alu_match}} & alu_fwd_val) |
                     ({32{rs1_bru_match}} & bru_fwd_val) |
                     ({32{rs1_lsu_match}} & lsu_fwd_val) 
                     ;  

assign rs2_alu_match = isq_rs2_type && rs2_index_map == alu_fwd_inst_id && alu_fwd_vld;
assign rs2_bru_match = isq_rs2_type && rs2_index_map == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld;
assign rs2_lsu_match = isq_rs2_type && rs2_index_map == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld;

assign rs2_fu_match = rs2_alu_match || rs2_bru_match || rs2_lsu_match;

assign rs2_fwd_val = ({32{rs2_alu_match}} & alu_fwd_val) |
                     ({32{rs2_bru_match}} & bru_fwd_val) |
                     ({32{rs2_lsu_match}} & lsu_fwd_val) 
                     ;  

// Operation Number Read
assign reg_rs1_rdy = ~isq_rs1_vld ||
                    (isq_rs1_vld && isq_rs1_rdy) ||
                    rs1_fu_match;

assign reg_rs2_rdy = ~isq_rs2_vld ||
                    (isq_rs2_vld && isq_rs2_rdy) ||
                    rs2_fu_match;

assign reg_rs1_val = ~isq_rs1_type ? rf_rs1_data :
                     rs1_fu_match ? rs1_fwd_val : rob_rs1_data;

assign reg_rs2_val = ~isq_rs2_type ? rf_rs2_data :
                     rs2_fu_match ? rs2_fwd_val : rob_rs2_data;

//ISQ Ready Control
assign isq_ready_nxt = entry_num < 16 - 2;
assign isq_full      = entry_num == 16;

//Register Value Read
assign rf_rs1_ind    = isq_rs1_ind[4:0];
assign rf_rs2_ind    = isq_rs2_ind[4:0];

assign rob_rs1_ind   = isq_rs1_ind;
assign rob_rs2_ind   = isq_rs2_ind;

//=============================================================================
//Instruction Dispatch
//=============================================================================
//ALU Entry Pick
assign alu_sel_0 = alue_req_0;
assign alu_sel_1 = alue_req_1;
assign alu_sel_2 = alue_req_2;
assign alu_sel_3 = alue_req_3;
assign alu_sel_4 = alue_req_4;
assign alu_sel_5 = alue_req_5;
assign alu_sel_6 = alue_req_6;
assign alu_sel_7 = alue_req_7;
assign alu_sel_8 = alue_req_8;
assign alu_sel_9 = alue_req_9;
assign alu_sel_10 = alue_req_10;
assign alu_sel_11 = alue_req_11;
assign alu_sel_12 = alue_req_12;
assign alu_sel_13 = alue_req_13;
assign alu_sel_14 = alue_req_14;
assign alu_sel_15 = alue_req_15;
// Dispatch the oldest ALU Ready Entry to ALU, and compute the result,this operaton can also wake up the related Instruction 
assign alu_req_nxt = alu_sel_0  
           | alu_sel_1
           | alu_sel_2
           | alu_sel_3
           | alu_sel_4
           | alu_sel_5
           | alu_sel_6
           | alu_sel_7
           | alu_sel_8
           | alu_sel_9
           | alu_sel_10
           | alu_sel_11
           | alu_sel_12
           | alu_sel_13
           | alu_sel_14
           | alu_sel_15
               ;
//ALU Pikcer
isq_age_picker alu_entry_picker (
.age_0              (alue_inst_id_0),
.sel_0              (alu_sel_0     ),
.age_1              (alue_inst_id_1),
.sel_1              (alu_sel_1     ),
.age_2              (alue_inst_id_2),
.sel_2              (alu_sel_2     ),
.age_3              (alue_inst_id_3),
.sel_3              (alu_sel_3     ),
.age_4              (alue_inst_id_4),
.sel_4              (alu_sel_4     ),
.age_5              (alue_inst_id_5),
.sel_5              (alu_sel_5     ),
.age_6              (alue_inst_id_6),
.sel_6              (alu_sel_6     ),
.age_7              (alue_inst_id_7),
.sel_7              (alu_sel_7     ),
.age_8              (alue_inst_id_8),
.sel_8              (alu_sel_8     ),
.age_9              (alue_inst_id_9),
.sel_9              (alu_sel_9     ),
.age_10              (alue_inst_id_10),
.sel_10              (alu_sel_10     ),
.age_11              (alue_inst_id_11),
.sel_11              (alu_sel_11     ),
.age_12              (alue_inst_id_12),
.sel_12              (alu_sel_12     ),
.age_13              (alue_inst_id_13),
.sel_13              (alu_sel_13     ),
.age_14              (alue_inst_id_14),
.sel_14              (alu_sel_14     ),
.age_15              (alue_inst_id_15),
.sel_15              (alu_sel_15     ),
.res_age              (alu_pick_inst_id),  
.res_index            (alu_pick_index)  
);

assign alu_inst_id_nxt     = alu_pick_inst_id;

assign alu_pick_vec_0 = alu_pick_index == 0 && alu_sel_0;
assign alu_pick_vec_1 = alu_pick_index == 1 && alu_sel_1;
assign alu_pick_vec_2 = alu_pick_index == 2 && alu_sel_2;
assign alu_pick_vec_3 = alu_pick_index == 3 && alu_sel_3;
assign alu_pick_vec_4 = alu_pick_index == 4 && alu_sel_4;
assign alu_pick_vec_5 = alu_pick_index == 5 && alu_sel_5;
assign alu_pick_vec_6 = alu_pick_index == 6 && alu_sel_6;
assign alu_pick_vec_7 = alu_pick_index == 7 && alu_sel_7;
assign alu_pick_vec_8 = alu_pick_index == 8 && alu_sel_8;
assign alu_pick_vec_9 = alu_pick_index == 9 && alu_sel_9;
assign alu_pick_vec_10 = alu_pick_index == 10 && alu_sel_10;
assign alu_pick_vec_11 = alu_pick_index == 11 && alu_sel_11;
assign alu_pick_vec_12 = alu_pick_index == 12 && alu_sel_12;
assign alu_pick_vec_13 = alu_pick_index == 13 && alu_sel_13;
assign alu_pick_vec_14 = alu_pick_index == 14 && alu_sel_14;
assign alu_pick_vec_15 = alu_pick_index == 15 && alu_sel_15;

assign alu_ctrl_land_nxt   = (alu_pick_vec_0 && alue_ctrl_land_0)
                     | (alu_pick_vec_1 && alue_ctrl_land_1)
                     | (alu_pick_vec_2 && alue_ctrl_land_2)
                     | (alu_pick_vec_3 && alue_ctrl_land_3)
                     | (alu_pick_vec_4 && alue_ctrl_land_4)
                     | (alu_pick_vec_5 && alue_ctrl_land_5)
                     | (alu_pick_vec_6 && alue_ctrl_land_6)
                     | (alu_pick_vec_7 && alue_ctrl_land_7)
                     | (alu_pick_vec_8 && alue_ctrl_land_8)
                     | (alu_pick_vec_9 && alue_ctrl_land_9)
                     | (alu_pick_vec_10 && alue_ctrl_land_10)
                     | (alu_pick_vec_11 && alue_ctrl_land_11)
                     | (alu_pick_vec_12 && alue_ctrl_land_12)
                     | (alu_pick_vec_13 && alue_ctrl_land_13)
                     | (alu_pick_vec_14 && alue_ctrl_land_14)
                     | (alu_pick_vec_15 && alue_ctrl_land_15)
                         ;

assign alu_ctrl_lor_nxt    = (alu_pick_vec_0 && alue_ctrl_lor_0)
                     | (alu_pick_vec_1 && alue_ctrl_lor_1)
                     | (alu_pick_vec_2 && alue_ctrl_lor_2)
                     | (alu_pick_vec_3 && alue_ctrl_lor_3)
                     | (alu_pick_vec_4 && alue_ctrl_lor_4)
                     | (alu_pick_vec_5 && alue_ctrl_lor_5)
                     | (alu_pick_vec_6 && alue_ctrl_lor_6)
                     | (alu_pick_vec_7 && alue_ctrl_lor_7)
                     | (alu_pick_vec_8 && alue_ctrl_lor_8)
                     | (alu_pick_vec_9 && alue_ctrl_lor_9)
                     | (alu_pick_vec_10 && alue_ctrl_lor_10)
                     | (alu_pick_vec_11 && alue_ctrl_lor_11)
                     | (alu_pick_vec_12 && alue_ctrl_lor_12)
                     | (alu_pick_vec_13 && alue_ctrl_lor_13)
                     | (alu_pick_vec_14 && alue_ctrl_lor_14)
                     | (alu_pick_vec_15 && alue_ctrl_lor_15)
                         ;

assign alu_ctrl_lxor_nxt   = (alu_pick_vec_0 && alue_ctrl_lxor_0)
                     | (alu_pick_vec_1 && alue_ctrl_lxor_1)
                     | (alu_pick_vec_2 && alue_ctrl_lxor_2)
                     | (alu_pick_vec_3 && alue_ctrl_lxor_3)
                     | (alu_pick_vec_4 && alue_ctrl_lxor_4)
                     | (alu_pick_vec_5 && alue_ctrl_lxor_5)
                     | (alu_pick_vec_6 && alue_ctrl_lxor_6)
                     | (alu_pick_vec_7 && alue_ctrl_lxor_7)
                     | (alu_pick_vec_8 && alue_ctrl_lxor_8)
                     | (alu_pick_vec_9 && alue_ctrl_lxor_9)
                     | (alu_pick_vec_10 && alue_ctrl_lxor_10)
                     | (alu_pick_vec_11 && alue_ctrl_lxor_11)
                     | (alu_pick_vec_12 && alue_ctrl_lxor_12)
                     | (alu_pick_vec_13 && alue_ctrl_lxor_13)
                     | (alu_pick_vec_14 && alue_ctrl_lxor_14)
                     | (alu_pick_vec_15 && alue_ctrl_lxor_15)
                         ;

assign alu_ctrl_sll_nxt    = (alu_pick_vec_0 && alue_ctrl_sll_0)
                     | (alu_pick_vec_1 && alue_ctrl_sll_1)
                     | (alu_pick_vec_2 && alue_ctrl_sll_2)
                     | (alu_pick_vec_3 && alue_ctrl_sll_3)
                     | (alu_pick_vec_4 && alue_ctrl_sll_4)
                     | (alu_pick_vec_5 && alue_ctrl_sll_5)
                     | (alu_pick_vec_6 && alue_ctrl_sll_6)
                     | (alu_pick_vec_7 && alue_ctrl_sll_7)
                     | (alu_pick_vec_8 && alue_ctrl_sll_8)
                     | (alu_pick_vec_9 && alue_ctrl_sll_9)
                     | (alu_pick_vec_10 && alue_ctrl_sll_10)
                     | (alu_pick_vec_11 && alue_ctrl_sll_11)
                     | (alu_pick_vec_12 && alue_ctrl_sll_12)
                     | (alu_pick_vec_13 && alue_ctrl_sll_13)
                     | (alu_pick_vec_14 && alue_ctrl_sll_14)
                     | (alu_pick_vec_15 && alue_ctrl_sll_15)
                         ;

assign alu_ctrl_srl_nxt    = (alu_pick_vec_0 && alue_ctrl_srl_0)
                     | (alu_pick_vec_1 && alue_ctrl_srl_1)
                     | (alu_pick_vec_2 && alue_ctrl_srl_2)
                     | (alu_pick_vec_3 && alue_ctrl_srl_3)
                     | (alu_pick_vec_4 && alue_ctrl_srl_4)
                     | (alu_pick_vec_5 && alue_ctrl_srl_5)
                     | (alu_pick_vec_6 && alue_ctrl_srl_6)
                     | (alu_pick_vec_7 && alue_ctrl_srl_7)
                     | (alu_pick_vec_8 && alue_ctrl_srl_8)
                     | (alu_pick_vec_9 && alue_ctrl_srl_9)
                     | (alu_pick_vec_10 && alue_ctrl_srl_10)
                     | (alu_pick_vec_11 && alue_ctrl_srl_11)
                     | (alu_pick_vec_12 && alue_ctrl_srl_12)
                     | (alu_pick_vec_13 && alue_ctrl_srl_13)
                     | (alu_pick_vec_14 && alue_ctrl_srl_14)
                     | (alu_pick_vec_15 && alue_ctrl_srl_15)
                         ;

assign alu_ctrl_sra_nxt    = (alu_pick_vec_0 && alue_ctrl_sra_0)
                     | (alu_pick_vec_1 && alue_ctrl_sra_1)
                     | (alu_pick_vec_2 && alue_ctrl_sra_2)
                     | (alu_pick_vec_3 && alue_ctrl_sra_3)
                     | (alu_pick_vec_4 && alue_ctrl_sra_4)
                     | (alu_pick_vec_5 && alue_ctrl_sra_5)
                     | (alu_pick_vec_6 && alue_ctrl_sra_6)
                     | (alu_pick_vec_7 && alue_ctrl_sra_7)
                     | (alu_pick_vec_8 && alue_ctrl_sra_8)
                     | (alu_pick_vec_9 && alue_ctrl_sra_9)
                     | (alu_pick_vec_10 && alue_ctrl_sra_10)
                     | (alu_pick_vec_11 && alue_ctrl_sra_11)
                     | (alu_pick_vec_12 && alue_ctrl_sra_12)
                     | (alu_pick_vec_13 && alue_ctrl_sra_13)
                     | (alu_pick_vec_14 && alue_ctrl_sra_14)
                     | (alu_pick_vec_15 && alue_ctrl_sra_15)
                         ;
 
assign alu_ctrl_add_nxt    = (alu_pick_vec_0 && alue_ctrl_add_0)
                     | (alu_pick_vec_1 && alue_ctrl_add_1)
                     | (alu_pick_vec_2 && alue_ctrl_add_2)
                     | (alu_pick_vec_3 && alue_ctrl_add_3)
                     | (alu_pick_vec_4 && alue_ctrl_add_4)
                     | (alu_pick_vec_5 && alue_ctrl_add_5)
                     | (alu_pick_vec_6 && alue_ctrl_add_6)
                     | (alu_pick_vec_7 && alue_ctrl_add_7)
                     | (alu_pick_vec_8 && alue_ctrl_add_8)
                     | (alu_pick_vec_9 && alue_ctrl_add_9)
                     | (alu_pick_vec_10 && alue_ctrl_add_10)
                     | (alu_pick_vec_11 && alue_ctrl_add_11)
                     | (alu_pick_vec_12 && alue_ctrl_add_12)
                     | (alu_pick_vec_13 && alue_ctrl_add_13)
                     | (alu_pick_vec_14 && alue_ctrl_add_14)
                     | (alu_pick_vec_15 && alue_ctrl_add_15)
                         ;

assign alu_ctrl_sub_nxt    = (alu_pick_vec_0 && alue_ctrl_sub_0)
                     | (alu_pick_vec_1 && alue_ctrl_sub_1)
                     | (alu_pick_vec_2 && alue_ctrl_sub_2)
                     | (alu_pick_vec_3 && alue_ctrl_sub_3)
                     | (alu_pick_vec_4 && alue_ctrl_sub_4)
                     | (alu_pick_vec_5 && alue_ctrl_sub_5)
                     | (alu_pick_vec_6 && alue_ctrl_sub_6)
                     | (alu_pick_vec_7 && alue_ctrl_sub_7)
                     | (alu_pick_vec_8 && alue_ctrl_sub_8)
                     | (alu_pick_vec_9 && alue_ctrl_sub_9)
                     | (alu_pick_vec_10 && alue_ctrl_sub_10)
                     | (alu_pick_vec_11 && alue_ctrl_sub_11)
                     | (alu_pick_vec_12 && alue_ctrl_sub_12)
                     | (alu_pick_vec_13 && alue_ctrl_sub_13)
                     | (alu_pick_vec_14 && alue_ctrl_sub_14)
                     | (alu_pick_vec_15 && alue_ctrl_sub_15)
                         ;

assign alu_ctrl_slt_nxt    = (alu_pick_vec_0 && alue_ctrl_slt_0)
                     | (alu_pick_vec_1 && alue_ctrl_slt_1)
                     | (alu_pick_vec_2 && alue_ctrl_slt_2)
                     | (alu_pick_vec_3 && alue_ctrl_slt_3)
                     | (alu_pick_vec_4 && alue_ctrl_slt_4)
                     | (alu_pick_vec_5 && alue_ctrl_slt_5)
                     | (alu_pick_vec_6 && alue_ctrl_slt_6)
                     | (alu_pick_vec_7 && alue_ctrl_slt_7)
                     | (alu_pick_vec_8 && alue_ctrl_slt_8)
                     | (alu_pick_vec_9 && alue_ctrl_slt_9)
                     | (alu_pick_vec_10 && alue_ctrl_slt_10)
                     | (alu_pick_vec_11 && alue_ctrl_slt_11)
                     | (alu_pick_vec_12 && alue_ctrl_slt_12)
                     | (alu_pick_vec_13 && alue_ctrl_slt_13)
                     | (alu_pick_vec_14 && alue_ctrl_slt_14)
                     | (alu_pick_vec_15 && alue_ctrl_slt_15)
                         ;

assign alu_ctrl_unsign_nxt = (alu_pick_vec_0 && alue_ctrl_unsign_0)
                     | (alu_pick_vec_1 && alue_ctrl_unsign_1)
                     | (alu_pick_vec_2 && alue_ctrl_unsign_2)
                     | (alu_pick_vec_3 && alue_ctrl_unsign_3)
                     | (alu_pick_vec_4 && alue_ctrl_unsign_4)
                     | (alu_pick_vec_5 && alue_ctrl_unsign_5)
                     | (alu_pick_vec_6 && alue_ctrl_unsign_6)
                     | (alu_pick_vec_7 && alue_ctrl_unsign_7)
                     | (alu_pick_vec_8 && alue_ctrl_unsign_8)
                     | (alu_pick_vec_9 && alue_ctrl_unsign_9)
                     | (alu_pick_vec_10 && alue_ctrl_unsign_10)
                     | (alu_pick_vec_11 && alue_ctrl_unsign_11)
                     | (alu_pick_vec_12 && alue_ctrl_unsign_12)
                     | (alu_pick_vec_13 && alue_ctrl_unsign_13)
                     | (alu_pick_vec_14 && alue_ctrl_unsign_14)
                     | (alu_pick_vec_15 && alue_ctrl_unsign_15)
                         ;

assign alu_op1_val_nxt     = ({32{alu_pick_vec_0}} & alue_op1_val_0)
                     | ({32{alu_pick_vec_1}} & alue_op1_val_1)
                     | ({32{alu_pick_vec_2}} & alue_op1_val_2)
                     | ({32{alu_pick_vec_3}} & alue_op1_val_3)
                     | ({32{alu_pick_vec_4}} & alue_op1_val_4)
                     | ({32{alu_pick_vec_5}} & alue_op1_val_5)
                     | ({32{alu_pick_vec_6}} & alue_op1_val_6)
                     | ({32{alu_pick_vec_7}} & alue_op1_val_7)
                     | ({32{alu_pick_vec_8}} & alue_op1_val_8)
                     | ({32{alu_pick_vec_9}} & alue_op1_val_9)
                     | ({32{alu_pick_vec_10}} & alue_op1_val_10)
                     | ({32{alu_pick_vec_11}} & alue_op1_val_11)
                     | ({32{alu_pick_vec_12}} & alue_op1_val_12)
                     | ({32{alu_pick_vec_13}} & alue_op1_val_13)
                     | ({32{alu_pick_vec_14}} & alue_op1_val_14)
                     | ({32{alu_pick_vec_15}} & alue_op1_val_15)
                         ;

assign alu_op2_val_nxt     = ({32{alu_pick_vec_0}} & alue_op2_val_0)
                     | ({32{alu_pick_vec_1}} & alue_op2_val_1)
                     | ({32{alu_pick_vec_2}} & alue_op2_val_2)
                     | ({32{alu_pick_vec_3}} & alue_op2_val_3)
                     | ({32{alu_pick_vec_4}} & alue_op2_val_4)
                     | ({32{alu_pick_vec_5}} & alue_op2_val_5)
                     | ({32{alu_pick_vec_6}} & alue_op2_val_6)
                     | ({32{alu_pick_vec_7}} & alue_op2_val_7)
                     | ({32{alu_pick_vec_8}} & alue_op2_val_8)
                     | ({32{alu_pick_vec_9}} & alue_op2_val_9)
                     | ({32{alu_pick_vec_10}} & alue_op2_val_10)
                     | ({32{alu_pick_vec_11}} & alue_op2_val_11)
                     | ({32{alu_pick_vec_12}} & alue_op2_val_12)
                     | ({32{alu_pick_vec_13}} & alue_op2_val_13)
                     | ({32{alu_pick_vec_14}} & alue_op2_val_14)
                     | ({32{alu_pick_vec_15}} & alue_op2_val_15)
                         ;

//=============================================================================
//BRU Pick
assign bru_sel_0 = (isqe_valid_0 && isqe_ready_0 && brue_req_0);
assign bru_sel_1 = (isqe_valid_1 && isqe_ready_1 && brue_req_1);
assign bru_sel_2 = (isqe_valid_2 && isqe_ready_2 && brue_req_2);
assign bru_sel_3 = (isqe_valid_3 && isqe_ready_3 && brue_req_3);
assign bru_sel_4 = (isqe_valid_4 && isqe_ready_4 && brue_req_4);
assign bru_sel_5 = (isqe_valid_5 && isqe_ready_5 && brue_req_5);
assign bru_sel_6 = (isqe_valid_6 && isqe_ready_6 && brue_req_6);
assign bru_sel_7 = (isqe_valid_7 && isqe_ready_7 && brue_req_7);
assign bru_sel_8 = (isqe_valid_8 && isqe_ready_8 && brue_req_8);
assign bru_sel_9 = (isqe_valid_9 && isqe_ready_9 && brue_req_9);
assign bru_sel_10 = (isqe_valid_10 && isqe_ready_10 && brue_req_10);
assign bru_sel_11 = (isqe_valid_11 && isqe_ready_11 && brue_req_11);
assign bru_sel_12 = (isqe_valid_12 && isqe_ready_12 && brue_req_12);
assign bru_sel_13 = (isqe_valid_13 && isqe_ready_13 && brue_req_13);
assign bru_sel_14 = (isqe_valid_14 && isqe_ready_14 && brue_req_14);
assign bru_sel_15 = (isqe_valid_15 && isqe_ready_15 && brue_req_15);
// Dispatch the oldest BRU Ready Entry to BRU, and compute the result,this operaton can also wake up the related Instruction 
assign bru_req_nxt = bru_sel_0   
           | bru_sel_1
           | bru_sel_2
           | bru_sel_3
           | bru_sel_4
           | bru_sel_5
           | bru_sel_6
           | bru_sel_7
           | bru_sel_8
           | bru_sel_9
           | bru_sel_10
           | bru_sel_11
           | bru_sel_12
           | bru_sel_13
           | bru_sel_14
           | bru_sel_15
               ;

//BRU Pikcer
isq_age_picker bru_entry_picker (
.age_0              (brue_inst_id_0),
.sel_0              (bru_sel_0     ),
.age_1              (brue_inst_id_1),
.sel_1              (bru_sel_1     ),
.age_2              (brue_inst_id_2),
.sel_2              (bru_sel_2     ),
.age_3              (brue_inst_id_3),
.sel_3              (bru_sel_3     ),
.age_4              (brue_inst_id_4),
.sel_4              (bru_sel_4     ),
.age_5              (brue_inst_id_5),
.sel_5              (bru_sel_5     ),
.age_6              (brue_inst_id_6),
.sel_6              (bru_sel_6     ),
.age_7              (brue_inst_id_7),
.sel_7              (bru_sel_7     ),
.age_8              (brue_inst_id_8),
.sel_8              (bru_sel_8     ),
.age_9              (brue_inst_id_9),
.sel_9              (bru_sel_9     ),
.age_10              (brue_inst_id_10),
.sel_10              (bru_sel_10     ),
.age_11              (brue_inst_id_11),
.sel_11              (bru_sel_11     ),
.age_12              (brue_inst_id_12),
.sel_12              (bru_sel_12     ),
.age_13              (brue_inst_id_13),
.sel_13              (bru_sel_13     ),
.age_14              (brue_inst_id_14),
.sel_14              (bru_sel_14     ),
.age_15              (brue_inst_id_15),
.sel_15              (bru_sel_15     ),
.res_age              (bru_pick_inst_id),  
.res_index            (bru_pick_index)  
);

assign bru_inst_id_nxt     = bru_pick_inst_id;

wire entry_bru_flush_en;
wire bru_flush_older;

rob_id_cmpo #(5+1) _bru_rob_id_cmpo(bru_fwd_inst_id,bru_pick_inst_id,bru_flush_older);
//The BRU Pick Result in ISQ is younger than the BRU Resp Instruction whose result is branch prediction error,abandene pick Result 
assign entry_bru_flush_en  = bru_flush_older && bru_flush && bru_fwd_vld;
//33
assign bru_pick_vec_0 = bru_pick_index == 0 && bru_sel_0;
assign bru_pick_vec_1 = bru_pick_index == 1 && bru_sel_1;
assign bru_pick_vec_2 = bru_pick_index == 2 && bru_sel_2;
assign bru_pick_vec_3 = bru_pick_index == 3 && bru_sel_3;
assign bru_pick_vec_4 = bru_pick_index == 4 && bru_sel_4;
assign bru_pick_vec_5 = bru_pick_index == 5 && bru_sel_5;
assign bru_pick_vec_6 = bru_pick_index == 6 && bru_sel_6;
assign bru_pick_vec_7 = bru_pick_index == 7 && bru_sel_7;
assign bru_pick_vec_8 = bru_pick_index == 8 && bru_sel_8;
assign bru_pick_vec_9 = bru_pick_index == 9 && bru_sel_9;
assign bru_pick_vec_10 = bru_pick_index == 10 && bru_sel_10;
assign bru_pick_vec_11 = bru_pick_index == 11 && bru_sel_11;
assign bru_pick_vec_12 = bru_pick_index == 12 && bru_sel_12;
assign bru_pick_vec_13 = bru_pick_index == 13 && bru_sel_13;
assign bru_pick_vec_14 = bru_pick_index == 14 && bru_sel_14;
assign bru_pick_vec_15 = bru_pick_index == 15 && bru_sel_15;

assign bru_ctrl_beq_nxt   = ~entry_bru_flush_en && (bru_pick_vec_0 && brue_ctrl_beq_0)
                     | (bru_pick_vec_1 && brue_ctrl_beq_1)
                     | (bru_pick_vec_2 && brue_ctrl_beq_2)
                     | (bru_pick_vec_3 && brue_ctrl_beq_3)
                     | (bru_pick_vec_4 && brue_ctrl_beq_4)
                     | (bru_pick_vec_5 && brue_ctrl_beq_5)
                     | (bru_pick_vec_6 && brue_ctrl_beq_6)
                     | (bru_pick_vec_7 && brue_ctrl_beq_7)
                     | (bru_pick_vec_8 && brue_ctrl_beq_8)
                     | (bru_pick_vec_9 && brue_ctrl_beq_9)
                     | (bru_pick_vec_10 && brue_ctrl_beq_10)
                     | (bru_pick_vec_11 && brue_ctrl_beq_11)
                     | (bru_pick_vec_12 && brue_ctrl_beq_12)
                     | (bru_pick_vec_13 && brue_ctrl_beq_13)
                     | (bru_pick_vec_14 && brue_ctrl_beq_14)
                     | (bru_pick_vec_15 && brue_ctrl_beq_15)
                         ;

assign bru_ctrl_bne_nxt    = (bru_pick_vec_0 && brue_ctrl_bne_0)
                     | (bru_pick_vec_1 && brue_ctrl_bne_1)
                     | (bru_pick_vec_2 && brue_ctrl_bne_2)
                     | (bru_pick_vec_3 && brue_ctrl_bne_3)
                     | (bru_pick_vec_4 && brue_ctrl_bne_4)
                     | (bru_pick_vec_5 && brue_ctrl_bne_5)
                     | (bru_pick_vec_6 && brue_ctrl_bne_6)
                     | (bru_pick_vec_7 && brue_ctrl_bne_7)
                     | (bru_pick_vec_8 && brue_ctrl_bne_8)
                     | (bru_pick_vec_9 && brue_ctrl_bne_9)
                     | (bru_pick_vec_10 && brue_ctrl_bne_10)
                     | (bru_pick_vec_11 && brue_ctrl_bne_11)
                     | (bru_pick_vec_12 && brue_ctrl_bne_12)
                     | (bru_pick_vec_13 && brue_ctrl_bne_13)
                     | (bru_pick_vec_14 && brue_ctrl_bne_14)
                     | (bru_pick_vec_15 && brue_ctrl_bne_15)
                         ;

assign bru_ctrl_blt_nxt    = (bru_pick_vec_0 && brue_ctrl_blt_0)
                     | (bru_pick_vec_1 && brue_ctrl_blt_1)
                     | (bru_pick_vec_2 && brue_ctrl_blt_2)
                     | (bru_pick_vec_3 && brue_ctrl_blt_3)
                     | (bru_pick_vec_4 && brue_ctrl_blt_4)
                     | (bru_pick_vec_5 && brue_ctrl_blt_5)
                     | (bru_pick_vec_6 && brue_ctrl_blt_6)
                     | (bru_pick_vec_7 && brue_ctrl_blt_7)
                     | (bru_pick_vec_8 && brue_ctrl_blt_8)
                     | (bru_pick_vec_9 && brue_ctrl_blt_9)
                     | (bru_pick_vec_10 && brue_ctrl_blt_10)
                     | (bru_pick_vec_11 && brue_ctrl_blt_11)
                     | (bru_pick_vec_12 && brue_ctrl_blt_12)
                     | (bru_pick_vec_13 && brue_ctrl_blt_13)
                     | (bru_pick_vec_14 && brue_ctrl_blt_14)
                     | (bru_pick_vec_15 && brue_ctrl_blt_15)
                         ;

assign bru_ctrl_bge_nxt    = (bru_pick_vec_0 && brue_ctrl_bge_0)
                     | (bru_pick_vec_1 && brue_ctrl_bge_1)
                     | (bru_pick_vec_2 && brue_ctrl_bge_2)
                     | (bru_pick_vec_3 && brue_ctrl_bge_3)
                     | (bru_pick_vec_4 && brue_ctrl_bge_4)
                     | (bru_pick_vec_5 && brue_ctrl_bge_5)
                     | (bru_pick_vec_6 && brue_ctrl_bge_6)
                     | (bru_pick_vec_7 && brue_ctrl_bge_7)
                     | (bru_pick_vec_8 && brue_ctrl_bge_8)
                     | (bru_pick_vec_9 && brue_ctrl_bge_9)
                     | (bru_pick_vec_10 && brue_ctrl_bge_10)
                     | (bru_pick_vec_11 && brue_ctrl_bge_11)
                     | (bru_pick_vec_12 && brue_ctrl_bge_12)
                     | (bru_pick_vec_13 && brue_ctrl_bge_13)
                     | (bru_pick_vec_14 && brue_ctrl_bge_14)
                     | (bru_pick_vec_15 && brue_ctrl_bge_15)
                         ;

assign bru_ctrl_jal_nxt    = (bru_pick_vec_0 && brue_ctrl_jal_0)
                     | (bru_pick_vec_1 && brue_ctrl_jal_1)
                     | (bru_pick_vec_2 && brue_ctrl_jal_2)
                     | (bru_pick_vec_3 && brue_ctrl_jal_3)
                     | (bru_pick_vec_4 && brue_ctrl_jal_4)
                     | (bru_pick_vec_5 && brue_ctrl_jal_5)
                     | (bru_pick_vec_6 && brue_ctrl_jal_6)
                     | (bru_pick_vec_7 && brue_ctrl_jal_7)
                     | (bru_pick_vec_8 && brue_ctrl_jal_8)
                     | (bru_pick_vec_9 && brue_ctrl_jal_9)
                     | (bru_pick_vec_10 && brue_ctrl_jal_10)
                     | (bru_pick_vec_11 && brue_ctrl_jal_11)
                     | (bru_pick_vec_12 && brue_ctrl_jal_12)
                     | (bru_pick_vec_13 && brue_ctrl_jal_13)
                     | (bru_pick_vec_14 && brue_ctrl_jal_14)
                     | (bru_pick_vec_15 && brue_ctrl_jal_15)
                         ;

assign bru_ctrl_jalr_nxt   = (bru_pick_vec_0 && brue_ctrl_jalr_0)
                     | (bru_pick_vec_1 && brue_ctrl_jalr_1)
                     | (bru_pick_vec_2 && brue_ctrl_jalr_2)
                     | (bru_pick_vec_3 && brue_ctrl_jalr_3)
                     | (bru_pick_vec_4 && brue_ctrl_jalr_4)
                     | (bru_pick_vec_5 && brue_ctrl_jalr_5)
                     | (bru_pick_vec_6 && brue_ctrl_jalr_6)
                     | (bru_pick_vec_7 && brue_ctrl_jalr_7)
                     | (bru_pick_vec_8 && brue_ctrl_jalr_8)
                     | (bru_pick_vec_9 && brue_ctrl_jalr_9)
                     | (bru_pick_vec_10 && brue_ctrl_jalr_10)
                     | (bru_pick_vec_11 && brue_ctrl_jalr_11)
                     | (bru_pick_vec_12 && brue_ctrl_jalr_12)
                     | (bru_pick_vec_13 && brue_ctrl_jalr_13)
                     | (bru_pick_vec_14 && brue_ctrl_jalr_14)
                     | (bru_pick_vec_15 && brue_ctrl_jalr_15)
                         ;

assign bru_rd_vld_nxt      = (bru_pick_vec_0 && brue_rd_vld_0)
                     | (bru_pick_vec_1 && brue_rd_vld_1)
                     | (bru_pick_vec_2 && brue_rd_vld_2)
                     | (bru_pick_vec_3 && brue_rd_vld_3)
                     | (bru_pick_vec_4 && brue_rd_vld_4)
                     | (bru_pick_vec_5 && brue_rd_vld_5)
                     | (bru_pick_vec_6 && brue_rd_vld_6)
                     | (bru_pick_vec_7 && brue_rd_vld_7)
                     | (bru_pick_vec_8 && brue_rd_vld_8)
                     | (bru_pick_vec_9 && brue_rd_vld_9)
                     | (bru_pick_vec_10 && brue_rd_vld_10)
                     | (bru_pick_vec_11 && brue_rd_vld_11)
                     | (bru_pick_vec_12 && brue_rd_vld_12)
                     | (bru_pick_vec_13 && brue_rd_vld_13)
                     | (bru_pick_vec_14 && brue_rd_vld_14)
                     | (bru_pick_vec_15 && brue_rd_vld_15)
                         ;

assign bru_op1_val_nxt     = ({32{bru_pick_vec_0}} & brue_op1_val_0)
                     | ({32{bru_pick_vec_1}} & brue_op1_val_1)
                     | ({32{bru_pick_vec_2}} & brue_op1_val_2)
                     | ({32{bru_pick_vec_3}} & brue_op1_val_3)
                     | ({32{bru_pick_vec_4}} & brue_op1_val_4)
                     | ({32{bru_pick_vec_5}} & brue_op1_val_5)
                     | ({32{bru_pick_vec_6}} & brue_op1_val_6)
                     | ({32{bru_pick_vec_7}} & brue_op1_val_7)
                     | ({32{bru_pick_vec_8}} & brue_op1_val_8)
                     | ({32{bru_pick_vec_9}} & brue_op1_val_9)
                     | ({32{bru_pick_vec_10}} & brue_op1_val_10)
                     | ({32{bru_pick_vec_11}} & brue_op1_val_11)
                     | ({32{bru_pick_vec_12}} & brue_op1_val_12)
                     | ({32{bru_pick_vec_13}} & brue_op1_val_13)
                     | ({32{bru_pick_vec_14}} & brue_op1_val_14)
                     | ({32{bru_pick_vec_15}} & brue_op1_val_15)
                         ;

assign bru_op2_val_nxt     = ({32{bru_pick_vec_0}} & brue_op2_val_0)
                     | ({32{bru_pick_vec_1}} & brue_op2_val_1)
                     | ({32{bru_pick_vec_2}} & brue_op2_val_2)
                     | ({32{bru_pick_vec_3}} & brue_op2_val_3)
                     | ({32{bru_pick_vec_4}} & brue_op2_val_4)
                     | ({32{bru_pick_vec_5}} & brue_op2_val_5)
                     | ({32{bru_pick_vec_6}} & brue_op2_val_6)
                     | ({32{bru_pick_vec_7}} & brue_op2_val_7)
                     | ({32{bru_pick_vec_8}} & brue_op2_val_8)
                     | ({32{bru_pick_vec_9}} & brue_op2_val_9)
                     | ({32{bru_pick_vec_10}} & brue_op2_val_10)
                     | ({32{bru_pick_vec_11}} & brue_op2_val_11)
                     | ({32{bru_pick_vec_12}} & brue_op2_val_12)
                     | ({32{bru_pick_vec_13}} & brue_op2_val_13)
                     | ({32{bru_pick_vec_14}} & brue_op2_val_14)
                     | ({32{bru_pick_vec_15}} & brue_op2_val_15)
                         ;

assign bru_imm_val_nxt     = ({32{bru_pick_vec_0}} & brue_imm_val_0)
                     | ({32{bru_pick_vec_1}} & brue_imm_val_1)
                     | ({32{bru_pick_vec_2}} & brue_imm_val_2)
                     | ({32{bru_pick_vec_3}} & brue_imm_val_3)
                     | ({32{bru_pick_vec_4}} & brue_imm_val_4)
                     | ({32{bru_pick_vec_5}} & brue_imm_val_5)
                     | ({32{bru_pick_vec_6}} & brue_imm_val_6)
                     | ({32{bru_pick_vec_7}} & brue_imm_val_7)
                     | ({32{bru_pick_vec_8}} & brue_imm_val_8)
                     | ({32{bru_pick_vec_9}} & brue_imm_val_9)
                     | ({32{bru_pick_vec_10}} & brue_imm_val_10)
                     | ({32{bru_pick_vec_11}} & brue_imm_val_11)
                     | ({32{bru_pick_vec_12}} & brue_imm_val_12)
                     | ({32{bru_pick_vec_13}} & brue_imm_val_13)
                     | ({32{bru_pick_vec_14}} & brue_imm_val_14)
                     | ({32{bru_pick_vec_15}} & brue_imm_val_15)
                         ;

assign bru_pc_data_nxt     = ({32{bru_pick_vec_0}} & brue_pc_data_0)
                     | ({32{bru_pick_vec_1}} & brue_pc_data_1)
                     | ({32{bru_pick_vec_2}} & brue_pc_data_2)
                     | ({32{bru_pick_vec_3}} & brue_pc_data_3)
                     | ({32{bru_pick_vec_4}} & brue_pc_data_4)
                     | ({32{bru_pick_vec_5}} & brue_pc_data_5)
                     | ({32{bru_pick_vec_6}} & brue_pc_data_6)
                     | ({32{bru_pick_vec_7}} & brue_pc_data_7)
                     | ({32{bru_pick_vec_8}} & brue_pc_data_8)
                     | ({32{bru_pick_vec_9}} & brue_pc_data_9)
                     | ({32{bru_pick_vec_10}} & brue_pc_data_10)
                     | ({32{bru_pick_vec_11}} & brue_pc_data_11)
                     | ({32{bru_pick_vec_12}} & brue_pc_data_12)
                     | ({32{bru_pick_vec_13}} & brue_pc_data_13)
                     | ({32{bru_pick_vec_14}} & brue_pc_data_14)
                     | ({32{bru_pick_vec_15}} & brue_pc_data_15)
                         ;

assign bru_bp_taddr_nxt    = ({32{bru_pick_vec_0}} & brue_bp_taddr_0)
                     | ({32{bru_pick_vec_1}} & brue_bp_taddr_1)
                     | ({32{bru_pick_vec_2}} & brue_bp_taddr_2)
                     | ({32{bru_pick_vec_3}} & brue_bp_taddr_3)
                     | ({32{bru_pick_vec_4}} & brue_bp_taddr_4)
                     | ({32{bru_pick_vec_5}} & brue_bp_taddr_5)
                     | ({32{bru_pick_vec_6}} & brue_bp_taddr_6)
                     | ({32{bru_pick_vec_7}} & brue_bp_taddr_7)
                     | ({32{bru_pick_vec_8}} & brue_bp_taddr_8)
                     | ({32{bru_pick_vec_9}} & brue_bp_taddr_9)
                     | ({32{bru_pick_vec_10}} & brue_bp_taddr_10)
                     | ({32{bru_pick_vec_11}} & brue_bp_taddr_11)
                     | ({32{bru_pick_vec_12}} & brue_bp_taddr_12)
                     | ({32{bru_pick_vec_13}} & brue_bp_taddr_13)
                     | ({32{bru_pick_vec_14}} & brue_bp_taddr_14)
                     | ({32{bru_pick_vec_15}} & brue_bp_taddr_15)
                         ;

assign bru_bp_taken_nxt   = (bru_pick_vec_0 && brue_bp_taken_0)
                     | (bru_pick_vec_1 && brue_bp_taken_1)
                     | (bru_pick_vec_2 && brue_bp_taken_2)
                     | (bru_pick_vec_3 && brue_bp_taken_3)
                     | (bru_pick_vec_4 && brue_bp_taken_4)
                     | (bru_pick_vec_5 && brue_bp_taken_5)
                     | (bru_pick_vec_6 && brue_bp_taken_6)
                     | (bru_pick_vec_7 && brue_bp_taken_7)
                     | (bru_pick_vec_8 && brue_bp_taken_8)
                     | (bru_pick_vec_9 && brue_bp_taken_9)
                     | (bru_pick_vec_10 && brue_bp_taken_10)
                     | (bru_pick_vec_11 && brue_bp_taken_11)
                     | (bru_pick_vec_12 && brue_bp_taken_12)
                     | (bru_pick_vec_13 && brue_bp_taken_13)
                     | (bru_pick_vec_14 && brue_bp_taken_14)
                     | (bru_pick_vec_15 && brue_bp_taken_15)
                         ;

assign bru_bp_bhtv_nxt   = ({4{bru_pick_vec_0}} & brue_bp_bhtv_0)
                     | ({4{bru_pick_vec_1}} & brue_bp_bhtv_1)
                     | ({4{bru_pick_vec_2}} & brue_bp_bhtv_2)
                     | ({4{bru_pick_vec_3}} & brue_bp_bhtv_3)
                     | ({4{bru_pick_vec_4}} & brue_bp_bhtv_4)
                     | ({4{bru_pick_vec_5}} & brue_bp_bhtv_5)
                     | ({4{bru_pick_vec_6}} & brue_bp_bhtv_6)
                     | ({4{bru_pick_vec_7}} & brue_bp_bhtv_7)
                     | ({4{bru_pick_vec_8}} & brue_bp_bhtv_8)
                     | ({4{bru_pick_vec_9}} & brue_bp_bhtv_9)
                     | ({4{bru_pick_vec_10}} & brue_bp_bhtv_10)
                     | ({4{bru_pick_vec_11}} & brue_bp_bhtv_11)
                     | ({4{bru_pick_vec_12}} & brue_bp_bhtv_12)
                     | ({4{bru_pick_vec_13}} & brue_bp_bhtv_13)
                     | ({4{bru_pick_vec_14}} & brue_bp_bhtv_14)
                     | ({4{bru_pick_vec_15}} & brue_bp_bhtv_15)
                         ;

assign bru_bp_phtv_nxt    = ({32{bru_pick_vec_0}} & brue_bp_phtv_0)
                     | ({32{bru_pick_vec_1}} & brue_bp_phtv_1)
                     | ({32{bru_pick_vec_2}} & brue_bp_phtv_2)
                     | ({32{bru_pick_vec_3}} & brue_bp_phtv_3)
                     | ({32{bru_pick_vec_4}} & brue_bp_phtv_4)
                     | ({32{bru_pick_vec_5}} & brue_bp_phtv_5)
                     | ({32{bru_pick_vec_6}} & brue_bp_phtv_6)
                     | ({32{bru_pick_vec_7}} & brue_bp_phtv_7)
                     | ({32{bru_pick_vec_8}} & brue_bp_phtv_8)
                     | ({32{bru_pick_vec_9}} & brue_bp_phtv_9)
                     | ({32{bru_pick_vec_10}} & brue_bp_phtv_10)
                     | ({32{bru_pick_vec_11}} & brue_bp_phtv_11)
                     | ({32{bru_pick_vec_12}} & brue_bp_phtv_12)
                     | ({32{bru_pick_vec_13}} & brue_bp_phtv_13)
                     | ({32{bru_pick_vec_14}} & brue_bp_phtv_14)
                     | ({32{bru_pick_vec_15}} & brue_bp_phtv_15)
                         ;
//=============================================================================
//LSU Pick

wire lsu_store_match_0;
wire lsu_load_older_0;
wire lsu_load_match_0;
wire lsu_store_match_1;
wire lsu_load_older_1;
wire lsu_load_match_1;
wire lsu_store_match_2;
wire lsu_load_older_2;
wire lsu_load_match_2;
wire lsu_store_match_3;
wire lsu_load_older_3;
wire lsu_load_match_3;
wire lsu_store_match_4;
wire lsu_load_older_4;
wire lsu_load_match_4;
wire lsu_store_match_5;
wire lsu_load_older_5;
wire lsu_load_match_5;
wire lsu_store_match_6;
wire lsu_load_older_6;
wire lsu_load_match_6;
wire lsu_store_match_7;
wire lsu_load_older_7;
wire lsu_load_match_7;
wire lsu_store_match_8;
wire lsu_load_older_8;
wire lsu_load_match_8;
wire lsu_store_match_9;
wire lsu_load_older_9;
wire lsu_load_match_9;
wire lsu_store_match_10;
wire lsu_load_older_10;
wire lsu_load_match_10;
wire lsu_store_match_11;
wire lsu_load_older_11;
wire lsu_load_match_11;
wire lsu_store_match_12;
wire lsu_load_older_12;
wire lsu_load_match_12;
wire lsu_store_match_13;
wire lsu_load_older_13;
wire lsu_load_match_13;
wire lsu_store_match_14;
wire lsu_load_older_14;
wire lsu_load_match_14;
wire lsu_store_match_15;
wire lsu_load_older_15;
wire lsu_load_match_15;

assign lsu_store_match_0 = lsue_req_0 && lsue_ctrl_store_0 && (lsue_inst_id_0 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_0(lsue_inst_id_0,sob_head_inst_id,lsu_load_older_0);
assign lsu_load_match_0 = lsue_req_0 && lsue_ctrl_load_0 && (lsu_load_older_0 || ~sob_head_vld);
assign lsu_sel_0 = isqe_valid_0 && isqe_ready_0 && (lsu_store_match_0 || lsu_load_match_0) && lsu_ready;
assign lsu_store_match_1 = lsue_req_1 && lsue_ctrl_store_1 && (lsue_inst_id_1 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_1(lsue_inst_id_1,sob_head_inst_id,lsu_load_older_1);
assign lsu_load_match_1 = lsue_req_1 && lsue_ctrl_load_1 && (lsu_load_older_1 || ~sob_head_vld);
assign lsu_sel_1 = isqe_valid_1 && isqe_ready_1 && (lsu_store_match_1 || lsu_load_match_1) && lsu_ready;
assign lsu_store_match_2 = lsue_req_2 && lsue_ctrl_store_2 && (lsue_inst_id_2 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_2(lsue_inst_id_2,sob_head_inst_id,lsu_load_older_2);
assign lsu_load_match_2 = lsue_req_2 && lsue_ctrl_load_2 && (lsu_load_older_2 || ~sob_head_vld);
assign lsu_sel_2 = isqe_valid_2 && isqe_ready_2 && (lsu_store_match_2 || lsu_load_match_2) && lsu_ready;
assign lsu_store_match_3 = lsue_req_3 && lsue_ctrl_store_3 && (lsue_inst_id_3 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_3(lsue_inst_id_3,sob_head_inst_id,lsu_load_older_3);
assign lsu_load_match_3 = lsue_req_3 && lsue_ctrl_load_3 && (lsu_load_older_3 || ~sob_head_vld);
assign lsu_sel_3 = isqe_valid_3 && isqe_ready_3 && (lsu_store_match_3 || lsu_load_match_3) && lsu_ready;
assign lsu_store_match_4 = lsue_req_4 && lsue_ctrl_store_4 && (lsue_inst_id_4 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_4(lsue_inst_id_4,sob_head_inst_id,lsu_load_older_4);
assign lsu_load_match_4 = lsue_req_4 && lsue_ctrl_load_4 && (lsu_load_older_4 || ~sob_head_vld);
assign lsu_sel_4 = isqe_valid_4 && isqe_ready_4 && (lsu_store_match_4 || lsu_load_match_4) && lsu_ready;
assign lsu_store_match_5 = lsue_req_5 && lsue_ctrl_store_5 && (lsue_inst_id_5 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_5(lsue_inst_id_5,sob_head_inst_id,lsu_load_older_5);
assign lsu_load_match_5 = lsue_req_5 && lsue_ctrl_load_5 && (lsu_load_older_5 || ~sob_head_vld);
assign lsu_sel_5 = isqe_valid_5 && isqe_ready_5 && (lsu_store_match_5 || lsu_load_match_5) && lsu_ready;
assign lsu_store_match_6 = lsue_req_6 && lsue_ctrl_store_6 && (lsue_inst_id_6 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_6(lsue_inst_id_6,sob_head_inst_id,lsu_load_older_6);
assign lsu_load_match_6 = lsue_req_6 && lsue_ctrl_load_6 && (lsu_load_older_6 || ~sob_head_vld);
assign lsu_sel_6 = isqe_valid_6 && isqe_ready_6 && (lsu_store_match_6 || lsu_load_match_6) && lsu_ready;
assign lsu_store_match_7 = lsue_req_7 && lsue_ctrl_store_7 && (lsue_inst_id_7 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_7(lsue_inst_id_7,sob_head_inst_id,lsu_load_older_7);
assign lsu_load_match_7 = lsue_req_7 && lsue_ctrl_load_7 && (lsu_load_older_7 || ~sob_head_vld);
assign lsu_sel_7 = isqe_valid_7 && isqe_ready_7 && (lsu_store_match_7 || lsu_load_match_7) && lsu_ready;
assign lsu_store_match_8 = lsue_req_8 && lsue_ctrl_store_8 && (lsue_inst_id_8 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_8(lsue_inst_id_8,sob_head_inst_id,lsu_load_older_8);
assign lsu_load_match_8 = lsue_req_8 && lsue_ctrl_load_8 && (lsu_load_older_8 || ~sob_head_vld);
assign lsu_sel_8 = isqe_valid_8 && isqe_ready_8 && (lsu_store_match_8 || lsu_load_match_8) && lsu_ready;
assign lsu_store_match_9 = lsue_req_9 && lsue_ctrl_store_9 && (lsue_inst_id_9 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_9(lsue_inst_id_9,sob_head_inst_id,lsu_load_older_9);
assign lsu_load_match_9 = lsue_req_9 && lsue_ctrl_load_9 && (lsu_load_older_9 || ~sob_head_vld);
assign lsu_sel_9 = isqe_valid_9 && isqe_ready_9 && (lsu_store_match_9 || lsu_load_match_9) && lsu_ready;
assign lsu_store_match_10 = lsue_req_10 && lsue_ctrl_store_10 && (lsue_inst_id_10 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_10(lsue_inst_id_10,sob_head_inst_id,lsu_load_older_10);
assign lsu_load_match_10 = lsue_req_10 && lsue_ctrl_load_10 && (lsu_load_older_10 || ~sob_head_vld);
assign lsu_sel_10 = isqe_valid_10 && isqe_ready_10 && (lsu_store_match_10 || lsu_load_match_10) && lsu_ready;
assign lsu_store_match_11 = lsue_req_11 && lsue_ctrl_store_11 && (lsue_inst_id_11 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_11(lsue_inst_id_11,sob_head_inst_id,lsu_load_older_11);
assign lsu_load_match_11 = lsue_req_11 && lsue_ctrl_load_11 && (lsu_load_older_11 || ~sob_head_vld);
assign lsu_sel_11 = isqe_valid_11 && isqe_ready_11 && (lsu_store_match_11 || lsu_load_match_11) && lsu_ready;
assign lsu_store_match_12 = lsue_req_12 && lsue_ctrl_store_12 && (lsue_inst_id_12 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_12(lsue_inst_id_12,sob_head_inst_id,lsu_load_older_12);
assign lsu_load_match_12 = lsue_req_12 && lsue_ctrl_load_12 && (lsu_load_older_12 || ~sob_head_vld);
assign lsu_sel_12 = isqe_valid_12 && isqe_ready_12 && (lsu_store_match_12 || lsu_load_match_12) && lsu_ready;
assign lsu_store_match_13 = lsue_req_13 && lsue_ctrl_store_13 && (lsue_inst_id_13 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_13(lsue_inst_id_13,sob_head_inst_id,lsu_load_older_13);
assign lsu_load_match_13 = lsue_req_13 && lsue_ctrl_load_13 && (lsu_load_older_13 || ~sob_head_vld);
assign lsu_sel_13 = isqe_valid_13 && isqe_ready_13 && (lsu_store_match_13 || lsu_load_match_13) && lsu_ready;
assign lsu_store_match_14 = lsue_req_14 && lsue_ctrl_store_14 && (lsue_inst_id_14 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_14(lsue_inst_id_14,sob_head_inst_id,lsu_load_older_14);
assign lsu_load_match_14 = lsue_req_14 && lsue_ctrl_load_14 && (lsu_load_older_14 || ~sob_head_vld);
assign lsu_sel_14 = isqe_valid_14 && isqe_ready_14 && (lsu_store_match_14 || lsu_load_match_14) && lsu_ready;
assign lsu_store_match_15 = lsue_req_15 && lsue_ctrl_store_15 && (lsue_inst_id_15 == sob_head_inst_id || ~sob_head_vld);
rob_id_cmpo #(5+1) lsu_load_age_cmpo_15(lsue_inst_id_15,sob_head_inst_id,lsu_load_older_15);
assign lsu_load_match_15 = lsue_req_15 && lsue_ctrl_load_15 && (lsu_load_older_15 || ~sob_head_vld);
assign lsu_sel_15 = isqe_valid_15 && isqe_ready_15 && (lsu_store_match_15 || lsu_load_match_15) && lsu_ready;

assign lsu_req_nxt = lsu_sel_0  
           | lsu_sel_1
           | lsu_sel_2
           | lsu_sel_3
           | lsu_sel_4
           | lsu_sel_5
           | lsu_sel_6
           | lsu_sel_7
           | lsu_sel_8
           | lsu_sel_9
           | lsu_sel_10
           | lsu_sel_11
           | lsu_sel_12
           | lsu_sel_13
           | lsu_sel_14
           | lsu_sel_15
               ;

//LSU Picker
isq_age_picker lsu_entry_picker (
.age_0              (lsue_inst_id_0),
.sel_0              (lsu_sel_0     ),
.age_1              (lsue_inst_id_1),
.sel_1              (lsu_sel_1     ),
.age_2              (lsue_inst_id_2),
.sel_2              (lsu_sel_2     ),
.age_3              (lsue_inst_id_3),
.sel_3              (lsu_sel_3     ),
.age_4              (lsue_inst_id_4),
.sel_4              (lsu_sel_4     ),
.age_5              (lsue_inst_id_5),
.sel_5              (lsu_sel_5     ),
.age_6              (lsue_inst_id_6),
.sel_6              (lsu_sel_6     ),
.age_7              (lsue_inst_id_7),
.sel_7              (lsu_sel_7     ),
.age_8              (lsue_inst_id_8),
.sel_8              (lsu_sel_8     ),
.age_9              (lsue_inst_id_9),
.sel_9              (lsu_sel_9     ),
.age_10              (lsue_inst_id_10),
.sel_10              (lsu_sel_10     ),
.age_11              (lsue_inst_id_11),
.sel_11              (lsu_sel_11     ),
.age_12              (lsue_inst_id_12),
.sel_12              (lsu_sel_12     ),
.age_13              (lsue_inst_id_13),
.sel_13              (lsu_sel_13     ),
.age_14              (lsue_inst_id_14),
.sel_14              (lsu_sel_14     ),
.age_15              (lsue_inst_id_15),
.sel_15              (lsu_sel_15     ),
.res_age              (lsu_pick_inst_id),  
.res_index            (lsu_pick_index)  
);

assign lsu_inst_id_nxt = lsu_pick_inst_id;

assign lsu_pick_vec_0 = (lsu_pick_index == 0) && lsu_sel_0;
assign lsu_pick_vec_1 = (lsu_pick_index == 1) && lsu_sel_1;
assign lsu_pick_vec_2 = (lsu_pick_index == 2) && lsu_sel_2;
assign lsu_pick_vec_3 = (lsu_pick_index == 3) && lsu_sel_3;
assign lsu_pick_vec_4 = (lsu_pick_index == 4) && lsu_sel_4;
assign lsu_pick_vec_5 = (lsu_pick_index == 5) && lsu_sel_5;
assign lsu_pick_vec_6 = (lsu_pick_index == 6) && lsu_sel_6;
assign lsu_pick_vec_7 = (lsu_pick_index == 7) && lsu_sel_7;
assign lsu_pick_vec_8 = (lsu_pick_index == 8) && lsu_sel_8;
assign lsu_pick_vec_9 = (lsu_pick_index == 9) && lsu_sel_9;
assign lsu_pick_vec_10 = (lsu_pick_index == 10) && lsu_sel_10;
assign lsu_pick_vec_11 = (lsu_pick_index == 11) && lsu_sel_11;
assign lsu_pick_vec_12 = (lsu_pick_index == 12) && lsu_sel_12;
assign lsu_pick_vec_13 = (lsu_pick_index == 13) && lsu_sel_13;
assign lsu_pick_vec_14 = (lsu_pick_index == 14) && lsu_sel_14;
assign lsu_pick_vec_15 = (lsu_pick_index == 15) && lsu_sel_15;

assign lsu_ctrl_unsign_nxt   = (lsu_pick_vec_0 && lsue_ctrl_unsign_0)
                     | (lsu_pick_vec_1 && lsue_ctrl_unsign_1)
                     | (lsu_pick_vec_2 && lsue_ctrl_unsign_2)
                     | (lsu_pick_vec_3 && lsue_ctrl_unsign_3)
                     | (lsu_pick_vec_4 && lsue_ctrl_unsign_4)
                     | (lsu_pick_vec_5 && lsue_ctrl_unsign_5)
                     | (lsu_pick_vec_6 && lsue_ctrl_unsign_6)
                     | (lsu_pick_vec_7 && lsue_ctrl_unsign_7)
                     | (lsu_pick_vec_8 && lsue_ctrl_unsign_8)
                     | (lsu_pick_vec_9 && lsue_ctrl_unsign_9)
                     | (lsu_pick_vec_10 && lsue_ctrl_unsign_10)
                     | (lsu_pick_vec_11 && lsue_ctrl_unsign_11)
                     | (lsu_pick_vec_12 && lsue_ctrl_unsign_12)
                     | (lsu_pick_vec_13 && lsue_ctrl_unsign_13)
                     | (lsu_pick_vec_14 && lsue_ctrl_unsign_14)
                     | (lsu_pick_vec_15 && lsue_ctrl_unsign_15)
                         ;

assign lsu_ctrl_load_nxt     = (lsu_pick_vec_0 && lsue_ctrl_load_0)
                     | (lsu_pick_vec_1 && lsue_ctrl_load_1)
                     | (lsu_pick_vec_2 && lsue_ctrl_load_2)
                     | (lsu_pick_vec_3 && lsue_ctrl_load_3)
                     | (lsu_pick_vec_4 && lsue_ctrl_load_4)
                     | (lsu_pick_vec_5 && lsue_ctrl_load_5)
                     | (lsu_pick_vec_6 && lsue_ctrl_load_6)
                     | (lsu_pick_vec_7 && lsue_ctrl_load_7)
                     | (lsu_pick_vec_8 && lsue_ctrl_load_8)
                     | (lsu_pick_vec_9 && lsue_ctrl_load_9)
                     | (lsu_pick_vec_10 && lsue_ctrl_load_10)
                     | (lsu_pick_vec_11 && lsue_ctrl_load_11)
                     | (lsu_pick_vec_12 && lsue_ctrl_load_12)
                     | (lsu_pick_vec_13 && lsue_ctrl_load_13)
                     | (lsu_pick_vec_14 && lsue_ctrl_load_14)
                     | (lsu_pick_vec_15 && lsue_ctrl_load_15)
                         ;

assign lsu_ctrl_store_nxt    = (lsu_pick_vec_0 && lsue_ctrl_store_0)
                     | (lsu_pick_vec_1 && lsue_ctrl_store_1)
                     | (lsu_pick_vec_2 && lsue_ctrl_store_2)
                     | (lsu_pick_vec_3 && lsue_ctrl_store_3)
                     | (lsu_pick_vec_4 && lsue_ctrl_store_4)
                     | (lsu_pick_vec_5 && lsue_ctrl_store_5)
                     | (lsu_pick_vec_6 && lsue_ctrl_store_6)
                     | (lsu_pick_vec_7 && lsue_ctrl_store_7)
                     | (lsu_pick_vec_8 && lsue_ctrl_store_8)
                     | (lsu_pick_vec_9 && lsue_ctrl_store_9)
                     | (lsu_pick_vec_10 && lsue_ctrl_store_10)
                     | (lsu_pick_vec_11 && lsue_ctrl_store_11)
                     | (lsu_pick_vec_12 && lsue_ctrl_store_12)
                     | (lsu_pick_vec_13 && lsue_ctrl_store_13)
                     | (lsu_pick_vec_14 && lsue_ctrl_store_14)
                     | (lsu_pick_vec_15 && lsue_ctrl_store_15)
                         ;

assign lsu_ctrl_word_nxt   = (lsu_pick_vec_0 && lsue_ctrl_word_0)
                     | (lsu_pick_vec_1 && lsue_ctrl_word_1)
                     | (lsu_pick_vec_2 && lsue_ctrl_word_2)
                     | (lsu_pick_vec_3 && lsue_ctrl_word_3)
                     | (lsu_pick_vec_4 && lsue_ctrl_word_4)
                     | (lsu_pick_vec_5 && lsue_ctrl_word_5)
                     | (lsu_pick_vec_6 && lsue_ctrl_word_6)
                     | (lsu_pick_vec_7 && lsue_ctrl_word_7)
                     | (lsu_pick_vec_8 && lsue_ctrl_word_8)
                     | (lsu_pick_vec_9 && lsue_ctrl_word_9)
                     | (lsu_pick_vec_10 && lsue_ctrl_word_10)
                     | (lsu_pick_vec_11 && lsue_ctrl_word_11)
                     | (lsu_pick_vec_12 && lsue_ctrl_word_12)
                     | (lsu_pick_vec_13 && lsue_ctrl_word_13)
                     | (lsu_pick_vec_14 && lsue_ctrl_word_14)
                     | (lsu_pick_vec_15 && lsue_ctrl_word_15)
                         ;

assign lsu_ctrl_half_nxt   = (lsu_pick_vec_0 && lsue_ctrl_half_0)
                     | (lsu_pick_vec_1 && lsue_ctrl_half_1)
                     | (lsu_pick_vec_2 && lsue_ctrl_half_2)
                     | (lsu_pick_vec_3 && lsue_ctrl_half_3)
                     | (lsu_pick_vec_4 && lsue_ctrl_half_4)
                     | (lsu_pick_vec_5 && lsue_ctrl_half_5)
                     | (lsu_pick_vec_6 && lsue_ctrl_half_6)
                     | (lsu_pick_vec_7 && lsue_ctrl_half_7)
                     | (lsu_pick_vec_8 && lsue_ctrl_half_8)
                     | (lsu_pick_vec_9 && lsue_ctrl_half_9)
                     | (lsu_pick_vec_10 && lsue_ctrl_half_10)
                     | (lsu_pick_vec_11 && lsue_ctrl_half_11)
                     | (lsu_pick_vec_12 && lsue_ctrl_half_12)
                     | (lsu_pick_vec_13 && lsue_ctrl_half_13)
                     | (lsu_pick_vec_14 && lsue_ctrl_half_14)
                     | (lsu_pick_vec_15 && lsue_ctrl_half_15)
                         ;

assign lsu_ctrl_byte_nxt   = (lsu_pick_vec_0 && lsue_ctrl_byte_0)
                     | (lsu_pick_vec_1 && lsue_ctrl_byte_1)
                     | (lsu_pick_vec_2 && lsue_ctrl_byte_2)
                     | (lsu_pick_vec_3 && lsue_ctrl_byte_3)
                     | (lsu_pick_vec_4 && lsue_ctrl_byte_4)
                     | (lsu_pick_vec_5 && lsue_ctrl_byte_5)
                     | (lsu_pick_vec_6 && lsue_ctrl_byte_6)
                     | (lsu_pick_vec_7 && lsue_ctrl_byte_7)
                     | (lsu_pick_vec_8 && lsue_ctrl_byte_8)
                     | (lsu_pick_vec_9 && lsue_ctrl_byte_9)
                     | (lsu_pick_vec_10 && lsue_ctrl_byte_10)
                     | (lsu_pick_vec_11 && lsue_ctrl_byte_11)
                     | (lsu_pick_vec_12 && lsue_ctrl_byte_12)
                     | (lsu_pick_vec_13 && lsue_ctrl_byte_13)
                     | (lsu_pick_vec_14 && lsue_ctrl_byte_14)
                     | (lsu_pick_vec_15 && lsue_ctrl_byte_15)
                         ;

assign lsu_op1_val_nxt      = ({32{lsu_pick_vec_0}} & lsue_op1_val_0)
                     | ({32{lsu_pick_vec_1}} & lsue_op1_val_1)
                     | ({32{lsu_pick_vec_2}} & lsue_op1_val_2)
                     | ({32{lsu_pick_vec_3}} & lsue_op1_val_3)
                     | ({32{lsu_pick_vec_4}} & lsue_op1_val_4)
                     | ({32{lsu_pick_vec_5}} & lsue_op1_val_5)
                     | ({32{lsu_pick_vec_6}} & lsue_op1_val_6)
                     | ({32{lsu_pick_vec_7}} & lsue_op1_val_7)
                     | ({32{lsu_pick_vec_8}} & lsue_op1_val_8)
                     | ({32{lsu_pick_vec_9}} & lsue_op1_val_9)
                     | ({32{lsu_pick_vec_10}} & lsue_op1_val_10)
                     | ({32{lsu_pick_vec_11}} & lsue_op1_val_11)
                     | ({32{lsu_pick_vec_12}} & lsue_op1_val_12)
                     | ({32{lsu_pick_vec_13}} & lsue_op1_val_13)
                     | ({32{lsu_pick_vec_14}} & lsue_op1_val_14)
                     | ({32{lsu_pick_vec_15}} & lsue_op1_val_15)
                         ;

assign lsu_op2_val_nxt     = ({32{lsu_pick_vec_0}} & lsue_op2_val_0)
                     | ({32{lsu_pick_vec_1}} & lsue_op2_val_1)
                     | ({32{lsu_pick_vec_2}} & lsue_op2_val_2)
                     | ({32{lsu_pick_vec_3}} & lsue_op2_val_3)
                     | ({32{lsu_pick_vec_4}} & lsue_op2_val_4)
                     | ({32{lsu_pick_vec_5}} & lsue_op2_val_5)
                     | ({32{lsu_pick_vec_6}} & lsue_op2_val_6)
                     | ({32{lsu_pick_vec_7}} & lsue_op2_val_7)
                     | ({32{lsu_pick_vec_8}} & lsue_op2_val_8)
                     | ({32{lsu_pick_vec_9}} & lsue_op2_val_9)
                     | ({32{lsu_pick_vec_10}} & lsue_op2_val_10)
                     | ({32{lsu_pick_vec_11}} & lsue_op2_val_11)
                     | ({32{lsu_pick_vec_12}} & lsue_op2_val_12)
                     | ({32{lsu_pick_vec_13}} & lsue_op2_val_13)
                     | ({32{lsu_pick_vec_14}} & lsue_op2_val_14)
                     | ({32{lsu_pick_vec_15}} & lsue_op2_val_15)
                         ;

assign lsu_store_data_nxt  = ({32{lsu_pick_vec_0}} & lsue_store_data_0)
                     | ({32{lsu_pick_vec_1}} & lsue_store_data_1)
                     | ({32{lsu_pick_vec_2}} & lsue_store_data_2)
                     | ({32{lsu_pick_vec_3}} & lsue_store_data_3)
                     | ({32{lsu_pick_vec_4}} & lsue_store_data_4)
                     | ({32{lsu_pick_vec_5}} & lsue_store_data_5)
                     | ({32{lsu_pick_vec_6}} & lsue_store_data_6)
                     | ({32{lsu_pick_vec_7}} & lsue_store_data_7)
                     | ({32{lsu_pick_vec_8}} & lsue_store_data_8)
                     | ({32{lsu_pick_vec_9}} & lsue_store_data_9)
                     | ({32{lsu_pick_vec_10}} & lsue_store_data_10)
                     | ({32{lsu_pick_vec_11}} & lsue_store_data_11)
                     | ({32{lsu_pick_vec_12}} & lsue_store_data_12)
                     | ({32{lsu_pick_vec_13}} & lsue_store_data_13)
                     | ({32{lsu_pick_vec_14}} & lsue_store_data_14)
                     | ({32{lsu_pick_vec_15}} & lsue_store_data_15)
                         ;



assign sob_wreq = isq_wreq && isq_lsu_vld && isq_lsu_store && ~isq_full;

assign sob_inst_id  = isq_inst_id;

assign sob_flush    = bru_flush;
assign sob_flush_id = bru_fwd_inst_id;

//The sob_rreq is hight once the Pick L/S Instruction is Store
assign sob_rreq     = lsu_ctrl_store_nxt && lsu_req_nxt;

frv_isq_sob _frv_isq_sob(  // Store Order Buffer
.clk                        (clk             ),
.rst_n                      (rst_n           ),
.pd_rst                     (pd_rst          ),
.sob_wreq                   (sob_wreq        ),
.sob_inst_id                (sob_inst_id     ),   
.sob_flush                  (sob_flush       ),
.sob_flush_id               (sob_flush_id    ),
.sob_head_inst_id           (sob_head_inst_id),
.sob_head_vld               (sob_head_vld    ),
.sob_rreq                   (sob_rreq        ),
.sob_rdy                    (sob_rdy         ) 
);

isq_entry_num_compute _isq_entry_num_compute(
.entry_vld_0        (isqe_valid_0),
.entry_vld_1        (isqe_valid_1),
.entry_vld_2        (isqe_valid_2),
.entry_vld_3        (isqe_valid_3),
.entry_vld_4        (isqe_valid_4),
.entry_vld_5        (isqe_valid_5),
.entry_vld_6        (isqe_valid_6),
.entry_vld_7        (isqe_valid_7),
.entry_vld_8        (isqe_valid_8),
.entry_vld_9        (isqe_valid_9),
.entry_vld_10        (isqe_valid_10),
.entry_vld_11        (isqe_valid_11),
.entry_vld_12        (isqe_valid_12),
.entry_vld_13        (isqe_valid_13),
.entry_vld_14        (isqe_valid_14),
.entry_vld_15        (isqe_valid_15),
.entry_num        (entry_num)
);

//=============================================================================
// ISQ Entries
frv_isq_entry _frv_isq_entry_0(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_0       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_0      ),
.isqe_valid         (isqe_valid_0      ),
.isqe_ready         (isqe_ready_0      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_0        ),
.alue_issue         (alu_pick_vec_0        ),
.alue_ctrl_land     (alue_ctrl_land_0  ),
.alue_ctrl_lor      (alue_ctrl_lor_0   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_0  ),
.alue_ctrl_sll      (alue_ctrl_sll_0   ),
.alue_ctrl_srl      (alue_ctrl_srl_0   ),
.alue_ctrl_sra      (alue_ctrl_sra_0   ),
.alue_ctrl_add      (alue_ctrl_add_0   ),
.alue_ctrl_sub      (alue_ctrl_sub_0   ),
.alue_ctrl_slt      (alue_ctrl_slt_0   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_0),
.alue_inst_id       (alue_inst_id_0    ),
.alue_op1_val       (alue_op1_val_0    ),
.alue_op2_val       (alue_op2_val_0    ),
//.alue_rd_ind        (alue_rd_ind_0     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_0        ),
.brue_issue         (bru_pick_vec_0    ),
.brue_ctrl_beq      (brue_ctrl_beq_0   ),
.brue_ctrl_bne      (brue_ctrl_bne_0   ),
.brue_ctrl_blt      (brue_ctrl_blt_0   ),
.brue_ctrl_bge      (brue_ctrl_bge_0   ),
.brue_ctrl_jal      (brue_ctrl_jal_0   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_0  ),
.brue_inst_id       (brue_inst_id_0    ),
.brue_pc_data       (brue_pc_data_0    ),
.brue_op1_val       (brue_op1_val_0    ),
.brue_op2_val       (brue_op2_val_0    ),
.brue_imm_val       (brue_imm_val_0    ),
//.brue_rd_ind        (brue_rd_ind_0     ),
.brue_rd_vld        (brue_rd_vld_0     ),
.brue_bp_taddr      (brue_bp_taddr_0   ),
.brue_bp_taken      (brue_bp_taken_0   ),
.brue_bp_bhtv       (brue_bp_bhtv_0    ),
.brue_bp_phtv       (brue_bp_phtv_0    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_0        ),
.lsue_issue         (lsu_pick_vec_0    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_0),
.lsue_ctrl_load     (lsue_ctrl_load_0  ),
.lsue_ctrl_store    (lsue_ctrl_store_0 ),
.lsue_ctrl_word     (lsue_ctrl_word_0  ),
.lsue_ctrl_half     (lsue_ctrl_half_0  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_0  ),
.lsue_inst_id       (lsue_inst_id_0    ),
.lsue_op1_val       (lsue_op1_val_0    ),
.lsue_op2_val       (lsue_op2_val_0    ),
.lsue_store_data    (lsue_store_data_0 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_1(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_1       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_1      ),
.isqe_valid         (isqe_valid_1      ),
.isqe_ready         (isqe_ready_1      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_1        ),
.alue_issue         (alu_pick_vec_1        ),
.alue_ctrl_land     (alue_ctrl_land_1  ),
.alue_ctrl_lor      (alue_ctrl_lor_1   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_1  ),
.alue_ctrl_sll      (alue_ctrl_sll_1   ),
.alue_ctrl_srl      (alue_ctrl_srl_1   ),
.alue_ctrl_sra      (alue_ctrl_sra_1   ),
.alue_ctrl_add      (alue_ctrl_add_1   ),
.alue_ctrl_sub      (alue_ctrl_sub_1   ),
.alue_ctrl_slt      (alue_ctrl_slt_1   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_1),
.alue_inst_id       (alue_inst_id_1    ),
.alue_op1_val       (alue_op1_val_1    ),
.alue_op2_val       (alue_op2_val_1    ),
//.alue_rd_ind        (alue_rd_ind_1     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_1        ),
.brue_issue         (bru_pick_vec_1    ),
.brue_ctrl_beq      (brue_ctrl_beq_1   ),
.brue_ctrl_bne      (brue_ctrl_bne_1   ),
.brue_ctrl_blt      (brue_ctrl_blt_1   ),
.brue_ctrl_bge      (brue_ctrl_bge_1   ),
.brue_ctrl_jal      (brue_ctrl_jal_1   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_1  ),
.brue_inst_id       (brue_inst_id_1    ),
.brue_pc_data       (brue_pc_data_1    ),
.brue_op1_val       (brue_op1_val_1    ),
.brue_op2_val       (brue_op2_val_1    ),
.brue_imm_val       (brue_imm_val_1    ),
//.brue_rd_ind        (brue_rd_ind_1     ),
.brue_rd_vld        (brue_rd_vld_1     ),
.brue_bp_taddr      (brue_bp_taddr_1   ),
.brue_bp_taken      (brue_bp_taken_1   ),
.brue_bp_bhtv       (brue_bp_bhtv_1    ),
.brue_bp_phtv       (brue_bp_phtv_1    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_1        ),
.lsue_issue         (lsu_pick_vec_1    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_1),
.lsue_ctrl_load     (lsue_ctrl_load_1  ),
.lsue_ctrl_store    (lsue_ctrl_store_1 ),
.lsue_ctrl_word     (lsue_ctrl_word_1  ),
.lsue_ctrl_half     (lsue_ctrl_half_1  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_1  ),
.lsue_inst_id       (lsue_inst_id_1    ),
.lsue_op1_val       (lsue_op1_val_1    ),
.lsue_op2_val       (lsue_op2_val_1    ),
.lsue_store_data    (lsue_store_data_1 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_2(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_2       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_2      ),
.isqe_valid         (isqe_valid_2      ),
.isqe_ready         (isqe_ready_2      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_2        ),
.alue_issue         (alu_pick_vec_2        ),
.alue_ctrl_land     (alue_ctrl_land_2  ),
.alue_ctrl_lor      (alue_ctrl_lor_2   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_2  ),
.alue_ctrl_sll      (alue_ctrl_sll_2   ),
.alue_ctrl_srl      (alue_ctrl_srl_2   ),
.alue_ctrl_sra      (alue_ctrl_sra_2   ),
.alue_ctrl_add      (alue_ctrl_add_2   ),
.alue_ctrl_sub      (alue_ctrl_sub_2   ),
.alue_ctrl_slt      (alue_ctrl_slt_2   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_2),
.alue_inst_id       (alue_inst_id_2    ),
.alue_op1_val       (alue_op1_val_2    ),
.alue_op2_val       (alue_op2_val_2    ),
//.alue_rd_ind        (alue_rd_ind_2     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_2        ),
.brue_issue         (bru_pick_vec_2    ),
.brue_ctrl_beq      (brue_ctrl_beq_2   ),
.brue_ctrl_bne      (brue_ctrl_bne_2   ),
.brue_ctrl_blt      (brue_ctrl_blt_2   ),
.brue_ctrl_bge      (brue_ctrl_bge_2   ),
.brue_ctrl_jal      (brue_ctrl_jal_2   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_2  ),
.brue_inst_id       (brue_inst_id_2    ),
.brue_pc_data       (brue_pc_data_2    ),
.brue_op1_val       (brue_op1_val_2    ),
.brue_op2_val       (brue_op2_val_2    ),
.brue_imm_val       (brue_imm_val_2    ),
//.brue_rd_ind        (brue_rd_ind_2     ),
.brue_rd_vld        (brue_rd_vld_2     ),
.brue_bp_taddr      (brue_bp_taddr_2   ),
.brue_bp_taken      (brue_bp_taken_2   ),
.brue_bp_bhtv       (brue_bp_bhtv_2    ),
.brue_bp_phtv       (brue_bp_phtv_2    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_2        ),
.lsue_issue         (lsu_pick_vec_2    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_2),
.lsue_ctrl_load     (lsue_ctrl_load_2  ),
.lsue_ctrl_store    (lsue_ctrl_store_2 ),
.lsue_ctrl_word     (lsue_ctrl_word_2  ),
.lsue_ctrl_half     (lsue_ctrl_half_2  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_2  ),
.lsue_inst_id       (lsue_inst_id_2    ),
.lsue_op1_val       (lsue_op1_val_2    ),
.lsue_op2_val       (lsue_op2_val_2    ),
.lsue_store_data    (lsue_store_data_2 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_3(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_3       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_3      ),
.isqe_valid         (isqe_valid_3      ),
.isqe_ready         (isqe_ready_3      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_3        ),
.alue_issue         (alu_pick_vec_3        ),
.alue_ctrl_land     (alue_ctrl_land_3  ),
.alue_ctrl_lor      (alue_ctrl_lor_3   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_3  ),
.alue_ctrl_sll      (alue_ctrl_sll_3   ),
.alue_ctrl_srl      (alue_ctrl_srl_3   ),
.alue_ctrl_sra      (alue_ctrl_sra_3   ),
.alue_ctrl_add      (alue_ctrl_add_3   ),
.alue_ctrl_sub      (alue_ctrl_sub_3   ),
.alue_ctrl_slt      (alue_ctrl_slt_3   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_3),
.alue_inst_id       (alue_inst_id_3    ),
.alue_op1_val       (alue_op1_val_3    ),
.alue_op2_val       (alue_op2_val_3    ),
//.alue_rd_ind        (alue_rd_ind_3     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_3        ),
.brue_issue         (bru_pick_vec_3    ),
.brue_ctrl_beq      (brue_ctrl_beq_3   ),
.brue_ctrl_bne      (brue_ctrl_bne_3   ),
.brue_ctrl_blt      (brue_ctrl_blt_3   ),
.brue_ctrl_bge      (brue_ctrl_bge_3   ),
.brue_ctrl_jal      (brue_ctrl_jal_3   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_3  ),
.brue_inst_id       (brue_inst_id_3    ),
.brue_pc_data       (brue_pc_data_3    ),
.brue_op1_val       (brue_op1_val_3    ),
.brue_op2_val       (brue_op2_val_3    ),
.brue_imm_val       (brue_imm_val_3    ),
//.brue_rd_ind        (brue_rd_ind_3     ),
.brue_rd_vld        (brue_rd_vld_3     ),
.brue_bp_taddr      (brue_bp_taddr_3   ),
.brue_bp_taken      (brue_bp_taken_3   ),
.brue_bp_bhtv       (brue_bp_bhtv_3    ),
.brue_bp_phtv       (brue_bp_phtv_3    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_3        ),
.lsue_issue         (lsu_pick_vec_3    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_3),
.lsue_ctrl_load     (lsue_ctrl_load_3  ),
.lsue_ctrl_store    (lsue_ctrl_store_3 ),
.lsue_ctrl_word     (lsue_ctrl_word_3  ),
.lsue_ctrl_half     (lsue_ctrl_half_3  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_3  ),
.lsue_inst_id       (lsue_inst_id_3    ),
.lsue_op1_val       (lsue_op1_val_3    ),
.lsue_op2_val       (lsue_op2_val_3    ),
.lsue_store_data    (lsue_store_data_3 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_4(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_4       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_4      ),
.isqe_valid         (isqe_valid_4      ),
.isqe_ready         (isqe_ready_4      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_4        ),
.alue_issue         (alu_pick_vec_4        ),
.alue_ctrl_land     (alue_ctrl_land_4  ),
.alue_ctrl_lor      (alue_ctrl_lor_4   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_4  ),
.alue_ctrl_sll      (alue_ctrl_sll_4   ),
.alue_ctrl_srl      (alue_ctrl_srl_4   ),
.alue_ctrl_sra      (alue_ctrl_sra_4   ),
.alue_ctrl_add      (alue_ctrl_add_4   ),
.alue_ctrl_sub      (alue_ctrl_sub_4   ),
.alue_ctrl_slt      (alue_ctrl_slt_4   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_4),
.alue_inst_id       (alue_inst_id_4    ),
.alue_op1_val       (alue_op1_val_4    ),
.alue_op2_val       (alue_op2_val_4    ),
//.alue_rd_ind        (alue_rd_ind_4     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_4        ),
.brue_issue         (bru_pick_vec_4    ),
.brue_ctrl_beq      (brue_ctrl_beq_4   ),
.brue_ctrl_bne      (brue_ctrl_bne_4   ),
.brue_ctrl_blt      (brue_ctrl_blt_4   ),
.brue_ctrl_bge      (brue_ctrl_bge_4   ),
.brue_ctrl_jal      (brue_ctrl_jal_4   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_4  ),
.brue_inst_id       (brue_inst_id_4    ),
.brue_pc_data       (brue_pc_data_4    ),
.brue_op1_val       (brue_op1_val_4    ),
.brue_op2_val       (brue_op2_val_4    ),
.brue_imm_val       (brue_imm_val_4    ),
//.brue_rd_ind        (brue_rd_ind_4     ),
.brue_rd_vld        (brue_rd_vld_4     ),
.brue_bp_taddr      (brue_bp_taddr_4   ),
.brue_bp_taken      (brue_bp_taken_4   ),
.brue_bp_bhtv       (brue_bp_bhtv_4    ),
.brue_bp_phtv       (brue_bp_phtv_4    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_4        ),
.lsue_issue         (lsu_pick_vec_4    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_4),
.lsue_ctrl_load     (lsue_ctrl_load_4  ),
.lsue_ctrl_store    (lsue_ctrl_store_4 ),
.lsue_ctrl_word     (lsue_ctrl_word_4  ),
.lsue_ctrl_half     (lsue_ctrl_half_4  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_4  ),
.lsue_inst_id       (lsue_inst_id_4    ),
.lsue_op1_val       (lsue_op1_val_4    ),
.lsue_op2_val       (lsue_op2_val_4    ),
.lsue_store_data    (lsue_store_data_4 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_5(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_5       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_5      ),
.isqe_valid         (isqe_valid_5      ),
.isqe_ready         (isqe_ready_5      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_5        ),
.alue_issue         (alu_pick_vec_5        ),
.alue_ctrl_land     (alue_ctrl_land_5  ),
.alue_ctrl_lor      (alue_ctrl_lor_5   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_5  ),
.alue_ctrl_sll      (alue_ctrl_sll_5   ),
.alue_ctrl_srl      (alue_ctrl_srl_5   ),
.alue_ctrl_sra      (alue_ctrl_sra_5   ),
.alue_ctrl_add      (alue_ctrl_add_5   ),
.alue_ctrl_sub      (alue_ctrl_sub_5   ),
.alue_ctrl_slt      (alue_ctrl_slt_5   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_5),
.alue_inst_id       (alue_inst_id_5    ),
.alue_op1_val       (alue_op1_val_5    ),
.alue_op2_val       (alue_op2_val_5    ),
//.alue_rd_ind        (alue_rd_ind_5     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_5        ),
.brue_issue         (bru_pick_vec_5    ),
.brue_ctrl_beq      (brue_ctrl_beq_5   ),
.brue_ctrl_bne      (brue_ctrl_bne_5   ),
.brue_ctrl_blt      (brue_ctrl_blt_5   ),
.brue_ctrl_bge      (brue_ctrl_bge_5   ),
.brue_ctrl_jal      (brue_ctrl_jal_5   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_5  ),
.brue_inst_id       (brue_inst_id_5    ),
.brue_pc_data       (brue_pc_data_5    ),
.brue_op1_val       (brue_op1_val_5    ),
.brue_op2_val       (brue_op2_val_5    ),
.brue_imm_val       (brue_imm_val_5    ),
//.brue_rd_ind        (brue_rd_ind_5     ),
.brue_rd_vld        (brue_rd_vld_5     ),
.brue_bp_taddr      (brue_bp_taddr_5   ),
.brue_bp_taken      (brue_bp_taken_5   ),
.brue_bp_bhtv       (brue_bp_bhtv_5    ),
.brue_bp_phtv       (brue_bp_phtv_5    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_5        ),
.lsue_issue         (lsu_pick_vec_5    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_5),
.lsue_ctrl_load     (lsue_ctrl_load_5  ),
.lsue_ctrl_store    (lsue_ctrl_store_5 ),
.lsue_ctrl_word     (lsue_ctrl_word_5  ),
.lsue_ctrl_half     (lsue_ctrl_half_5  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_5  ),
.lsue_inst_id       (lsue_inst_id_5    ),
.lsue_op1_val       (lsue_op1_val_5    ),
.lsue_op2_val       (lsue_op2_val_5    ),
.lsue_store_data    (lsue_store_data_5 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_6(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_6       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_6      ),
.isqe_valid         (isqe_valid_6      ),
.isqe_ready         (isqe_ready_6      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_6        ),
.alue_issue         (alu_pick_vec_6        ),
.alue_ctrl_land     (alue_ctrl_land_6  ),
.alue_ctrl_lor      (alue_ctrl_lor_6   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_6  ),
.alue_ctrl_sll      (alue_ctrl_sll_6   ),
.alue_ctrl_srl      (alue_ctrl_srl_6   ),
.alue_ctrl_sra      (alue_ctrl_sra_6   ),
.alue_ctrl_add      (alue_ctrl_add_6   ),
.alue_ctrl_sub      (alue_ctrl_sub_6   ),
.alue_ctrl_slt      (alue_ctrl_slt_6   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_6),
.alue_inst_id       (alue_inst_id_6    ),
.alue_op1_val       (alue_op1_val_6    ),
.alue_op2_val       (alue_op2_val_6    ),
//.alue_rd_ind        (alue_rd_ind_6     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_6        ),
.brue_issue         (bru_pick_vec_6    ),
.brue_ctrl_beq      (brue_ctrl_beq_6   ),
.brue_ctrl_bne      (brue_ctrl_bne_6   ),
.brue_ctrl_blt      (brue_ctrl_blt_6   ),
.brue_ctrl_bge      (brue_ctrl_bge_6   ),
.brue_ctrl_jal      (brue_ctrl_jal_6   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_6  ),
.brue_inst_id       (brue_inst_id_6    ),
.brue_pc_data       (brue_pc_data_6    ),
.brue_op1_val       (brue_op1_val_6    ),
.brue_op2_val       (brue_op2_val_6    ),
.brue_imm_val       (brue_imm_val_6    ),
//.brue_rd_ind        (brue_rd_ind_6     ),
.brue_rd_vld        (brue_rd_vld_6     ),
.brue_bp_taddr      (brue_bp_taddr_6   ),
.brue_bp_taken      (brue_bp_taken_6   ),
.brue_bp_bhtv       (brue_bp_bhtv_6    ),
.brue_bp_phtv       (brue_bp_phtv_6    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_6        ),
.lsue_issue         (lsu_pick_vec_6    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_6),
.lsue_ctrl_load     (lsue_ctrl_load_6  ),
.lsue_ctrl_store    (lsue_ctrl_store_6 ),
.lsue_ctrl_word     (lsue_ctrl_word_6  ),
.lsue_ctrl_half     (lsue_ctrl_half_6  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_6  ),
.lsue_inst_id       (lsue_inst_id_6    ),
.lsue_op1_val       (lsue_op1_val_6    ),
.lsue_op2_val       (lsue_op2_val_6    ),
.lsue_store_data    (lsue_store_data_6 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_7(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_7       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_7      ),
.isqe_valid         (isqe_valid_7      ),
.isqe_ready         (isqe_ready_7      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_7        ),
.alue_issue         (alu_pick_vec_7        ),
.alue_ctrl_land     (alue_ctrl_land_7  ),
.alue_ctrl_lor      (alue_ctrl_lor_7   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_7  ),
.alue_ctrl_sll      (alue_ctrl_sll_7   ),
.alue_ctrl_srl      (alue_ctrl_srl_7   ),
.alue_ctrl_sra      (alue_ctrl_sra_7   ),
.alue_ctrl_add      (alue_ctrl_add_7   ),
.alue_ctrl_sub      (alue_ctrl_sub_7   ),
.alue_ctrl_slt      (alue_ctrl_slt_7   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_7),
.alue_inst_id       (alue_inst_id_7    ),
.alue_op1_val       (alue_op1_val_7    ),
.alue_op2_val       (alue_op2_val_7    ),
//.alue_rd_ind        (alue_rd_ind_7     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_7        ),
.brue_issue         (bru_pick_vec_7    ),
.brue_ctrl_beq      (brue_ctrl_beq_7   ),
.brue_ctrl_bne      (brue_ctrl_bne_7   ),
.brue_ctrl_blt      (brue_ctrl_blt_7   ),
.brue_ctrl_bge      (brue_ctrl_bge_7   ),
.brue_ctrl_jal      (brue_ctrl_jal_7   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_7  ),
.brue_inst_id       (brue_inst_id_7    ),
.brue_pc_data       (brue_pc_data_7    ),
.brue_op1_val       (brue_op1_val_7    ),
.brue_op2_val       (brue_op2_val_7    ),
.brue_imm_val       (brue_imm_val_7    ),
//.brue_rd_ind        (brue_rd_ind_7     ),
.brue_rd_vld        (brue_rd_vld_7     ),
.brue_bp_taddr      (brue_bp_taddr_7   ),
.brue_bp_taken      (brue_bp_taken_7   ),
.brue_bp_bhtv       (brue_bp_bhtv_7    ),
.brue_bp_phtv       (brue_bp_phtv_7    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_7        ),
.lsue_issue         (lsu_pick_vec_7    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_7),
.lsue_ctrl_load     (lsue_ctrl_load_7  ),
.lsue_ctrl_store    (lsue_ctrl_store_7 ),
.lsue_ctrl_word     (lsue_ctrl_word_7  ),
.lsue_ctrl_half     (lsue_ctrl_half_7  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_7  ),
.lsue_inst_id       (lsue_inst_id_7    ),
.lsue_op1_val       (lsue_op1_val_7    ),
.lsue_op2_val       (lsue_op2_val_7    ),
.lsue_store_data    (lsue_store_data_7 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_8(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_8       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_8      ),
.isqe_valid         (isqe_valid_8      ),
.isqe_ready         (isqe_ready_8      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_8        ),
.alue_issue         (alu_pick_vec_8        ),
.alue_ctrl_land     (alue_ctrl_land_8  ),
.alue_ctrl_lor      (alue_ctrl_lor_8   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_8  ),
.alue_ctrl_sll      (alue_ctrl_sll_8   ),
.alue_ctrl_srl      (alue_ctrl_srl_8   ),
.alue_ctrl_sra      (alue_ctrl_sra_8   ),
.alue_ctrl_add      (alue_ctrl_add_8   ),
.alue_ctrl_sub      (alue_ctrl_sub_8   ),
.alue_ctrl_slt      (alue_ctrl_slt_8   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_8),
.alue_inst_id       (alue_inst_id_8    ),
.alue_op1_val       (alue_op1_val_8    ),
.alue_op2_val       (alue_op2_val_8    ),
//.alue_rd_ind        (alue_rd_ind_8     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_8        ),
.brue_issue         (bru_pick_vec_8    ),
.brue_ctrl_beq      (brue_ctrl_beq_8   ),
.brue_ctrl_bne      (brue_ctrl_bne_8   ),
.brue_ctrl_blt      (brue_ctrl_blt_8   ),
.brue_ctrl_bge      (brue_ctrl_bge_8   ),
.brue_ctrl_jal      (brue_ctrl_jal_8   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_8  ),
.brue_inst_id       (brue_inst_id_8    ),
.brue_pc_data       (brue_pc_data_8    ),
.brue_op1_val       (brue_op1_val_8    ),
.brue_op2_val       (brue_op2_val_8    ),
.brue_imm_val       (brue_imm_val_8    ),
//.brue_rd_ind        (brue_rd_ind_8     ),
.brue_rd_vld        (brue_rd_vld_8     ),
.brue_bp_taddr      (brue_bp_taddr_8   ),
.brue_bp_taken      (brue_bp_taken_8   ),
.brue_bp_bhtv       (brue_bp_bhtv_8    ),
.brue_bp_phtv       (brue_bp_phtv_8    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_8        ),
.lsue_issue         (lsu_pick_vec_8    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_8),
.lsue_ctrl_load     (lsue_ctrl_load_8  ),
.lsue_ctrl_store    (lsue_ctrl_store_8 ),
.lsue_ctrl_word     (lsue_ctrl_word_8  ),
.lsue_ctrl_half     (lsue_ctrl_half_8  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_8  ),
.lsue_inst_id       (lsue_inst_id_8    ),
.lsue_op1_val       (lsue_op1_val_8    ),
.lsue_op2_val       (lsue_op2_val_8    ),
.lsue_store_data    (lsue_store_data_8 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_9(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_9       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_9      ),
.isqe_valid         (isqe_valid_9      ),
.isqe_ready         (isqe_ready_9      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_9        ),
.alue_issue         (alu_pick_vec_9        ),
.alue_ctrl_land     (alue_ctrl_land_9  ),
.alue_ctrl_lor      (alue_ctrl_lor_9   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_9  ),
.alue_ctrl_sll      (alue_ctrl_sll_9   ),
.alue_ctrl_srl      (alue_ctrl_srl_9   ),
.alue_ctrl_sra      (alue_ctrl_sra_9   ),
.alue_ctrl_add      (alue_ctrl_add_9   ),
.alue_ctrl_sub      (alue_ctrl_sub_9   ),
.alue_ctrl_slt      (alue_ctrl_slt_9   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_9),
.alue_inst_id       (alue_inst_id_9    ),
.alue_op1_val       (alue_op1_val_9    ),
.alue_op2_val       (alue_op2_val_9    ),
//.alue_rd_ind        (alue_rd_ind_9     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_9        ),
.brue_issue         (bru_pick_vec_9    ),
.brue_ctrl_beq      (brue_ctrl_beq_9   ),
.brue_ctrl_bne      (brue_ctrl_bne_9   ),
.brue_ctrl_blt      (brue_ctrl_blt_9   ),
.brue_ctrl_bge      (brue_ctrl_bge_9   ),
.brue_ctrl_jal      (brue_ctrl_jal_9   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_9  ),
.brue_inst_id       (brue_inst_id_9    ),
.brue_pc_data       (brue_pc_data_9    ),
.brue_op1_val       (brue_op1_val_9    ),
.brue_op2_val       (brue_op2_val_9    ),
.brue_imm_val       (brue_imm_val_9    ),
//.brue_rd_ind        (brue_rd_ind_9     ),
.brue_rd_vld        (brue_rd_vld_9     ),
.brue_bp_taddr      (brue_bp_taddr_9   ),
.brue_bp_taken      (brue_bp_taken_9   ),
.brue_bp_bhtv       (brue_bp_bhtv_9    ),
.brue_bp_phtv       (brue_bp_phtv_9    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_9        ),
.lsue_issue         (lsu_pick_vec_9    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_9),
.lsue_ctrl_load     (lsue_ctrl_load_9  ),
.lsue_ctrl_store    (lsue_ctrl_store_9 ),
.lsue_ctrl_word     (lsue_ctrl_word_9  ),
.lsue_ctrl_half     (lsue_ctrl_half_9  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_9  ),
.lsue_inst_id       (lsue_inst_id_9    ),
.lsue_op1_val       (lsue_op1_val_9    ),
.lsue_op2_val       (lsue_op2_val_9    ),
.lsue_store_data    (lsue_store_data_9 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_10(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_10       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_10      ),
.isqe_valid         (isqe_valid_10      ),
.isqe_ready         (isqe_ready_10      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_10        ),
.alue_issue         (alu_pick_vec_10        ),
.alue_ctrl_land     (alue_ctrl_land_10  ),
.alue_ctrl_lor      (alue_ctrl_lor_10   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_10  ),
.alue_ctrl_sll      (alue_ctrl_sll_10   ),
.alue_ctrl_srl      (alue_ctrl_srl_10   ),
.alue_ctrl_sra      (alue_ctrl_sra_10   ),
.alue_ctrl_add      (alue_ctrl_add_10   ),
.alue_ctrl_sub      (alue_ctrl_sub_10   ),
.alue_ctrl_slt      (alue_ctrl_slt_10   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_10),
.alue_inst_id       (alue_inst_id_10    ),
.alue_op1_val       (alue_op1_val_10    ),
.alue_op2_val       (alue_op2_val_10    ),
//.alue_rd_ind        (alue_rd_ind_10     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_10        ),
.brue_issue         (bru_pick_vec_10    ),
.brue_ctrl_beq      (brue_ctrl_beq_10   ),
.brue_ctrl_bne      (brue_ctrl_bne_10   ),
.brue_ctrl_blt      (brue_ctrl_blt_10   ),
.brue_ctrl_bge      (brue_ctrl_bge_10   ),
.brue_ctrl_jal      (brue_ctrl_jal_10   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_10  ),
.brue_inst_id       (brue_inst_id_10    ),
.brue_pc_data       (brue_pc_data_10    ),
.brue_op1_val       (brue_op1_val_10    ),
.brue_op2_val       (brue_op2_val_10    ),
.brue_imm_val       (brue_imm_val_10    ),
//.brue_rd_ind        (brue_rd_ind_10     ),
.brue_rd_vld        (brue_rd_vld_10     ),
.brue_bp_taddr      (brue_bp_taddr_10   ),
.brue_bp_taken      (brue_bp_taken_10   ),
.brue_bp_bhtv       (brue_bp_bhtv_10    ),
.brue_bp_phtv       (brue_bp_phtv_10    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_10        ),
.lsue_issue         (lsu_pick_vec_10    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_10),
.lsue_ctrl_load     (lsue_ctrl_load_10  ),
.lsue_ctrl_store    (lsue_ctrl_store_10 ),
.lsue_ctrl_word     (lsue_ctrl_word_10  ),
.lsue_ctrl_half     (lsue_ctrl_half_10  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_10  ),
.lsue_inst_id       (lsue_inst_id_10    ),
.lsue_op1_val       (lsue_op1_val_10    ),
.lsue_op2_val       (lsue_op2_val_10    ),
.lsue_store_data    (lsue_store_data_10 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_11(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_11       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_11      ),
.isqe_valid         (isqe_valid_11      ),
.isqe_ready         (isqe_ready_11      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_11        ),
.alue_issue         (alu_pick_vec_11        ),
.alue_ctrl_land     (alue_ctrl_land_11  ),
.alue_ctrl_lor      (alue_ctrl_lor_11   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_11  ),
.alue_ctrl_sll      (alue_ctrl_sll_11   ),
.alue_ctrl_srl      (alue_ctrl_srl_11   ),
.alue_ctrl_sra      (alue_ctrl_sra_11   ),
.alue_ctrl_add      (alue_ctrl_add_11   ),
.alue_ctrl_sub      (alue_ctrl_sub_11   ),
.alue_ctrl_slt      (alue_ctrl_slt_11   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_11),
.alue_inst_id       (alue_inst_id_11    ),
.alue_op1_val       (alue_op1_val_11    ),
.alue_op2_val       (alue_op2_val_11    ),
//.alue_rd_ind        (alue_rd_ind_11     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_11        ),
.brue_issue         (bru_pick_vec_11    ),
.brue_ctrl_beq      (brue_ctrl_beq_11   ),
.brue_ctrl_bne      (brue_ctrl_bne_11   ),
.brue_ctrl_blt      (brue_ctrl_blt_11   ),
.brue_ctrl_bge      (brue_ctrl_bge_11   ),
.brue_ctrl_jal      (brue_ctrl_jal_11   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_11  ),
.brue_inst_id       (brue_inst_id_11    ),
.brue_pc_data       (brue_pc_data_11    ),
.brue_op1_val       (brue_op1_val_11    ),
.brue_op2_val       (brue_op2_val_11    ),
.brue_imm_val       (brue_imm_val_11    ),
//.brue_rd_ind        (brue_rd_ind_11     ),
.brue_rd_vld        (brue_rd_vld_11     ),
.brue_bp_taddr      (brue_bp_taddr_11   ),
.brue_bp_taken      (brue_bp_taken_11   ),
.brue_bp_bhtv       (brue_bp_bhtv_11    ),
.brue_bp_phtv       (brue_bp_phtv_11    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_11        ),
.lsue_issue         (lsu_pick_vec_11    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_11),
.lsue_ctrl_load     (lsue_ctrl_load_11  ),
.lsue_ctrl_store    (lsue_ctrl_store_11 ),
.lsue_ctrl_word     (lsue_ctrl_word_11  ),
.lsue_ctrl_half     (lsue_ctrl_half_11  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_11  ),
.lsue_inst_id       (lsue_inst_id_11    ),
.lsue_op1_val       (lsue_op1_val_11    ),
.lsue_op2_val       (lsue_op2_val_11    ),
.lsue_store_data    (lsue_store_data_11 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_12(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_12       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_12      ),
.isqe_valid         (isqe_valid_12      ),
.isqe_ready         (isqe_ready_12      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_12        ),
.alue_issue         (alu_pick_vec_12        ),
.alue_ctrl_land     (alue_ctrl_land_12  ),
.alue_ctrl_lor      (alue_ctrl_lor_12   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_12  ),
.alue_ctrl_sll      (alue_ctrl_sll_12   ),
.alue_ctrl_srl      (alue_ctrl_srl_12   ),
.alue_ctrl_sra      (alue_ctrl_sra_12   ),
.alue_ctrl_add      (alue_ctrl_add_12   ),
.alue_ctrl_sub      (alue_ctrl_sub_12   ),
.alue_ctrl_slt      (alue_ctrl_slt_12   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_12),
.alue_inst_id       (alue_inst_id_12    ),
.alue_op1_val       (alue_op1_val_12    ),
.alue_op2_val       (alue_op2_val_12    ),
//.alue_rd_ind        (alue_rd_ind_12     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_12        ),
.brue_issue         (bru_pick_vec_12    ),
.brue_ctrl_beq      (brue_ctrl_beq_12   ),
.brue_ctrl_bne      (brue_ctrl_bne_12   ),
.brue_ctrl_blt      (brue_ctrl_blt_12   ),
.brue_ctrl_bge      (brue_ctrl_bge_12   ),
.brue_ctrl_jal      (brue_ctrl_jal_12   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_12  ),
.brue_inst_id       (brue_inst_id_12    ),
.brue_pc_data       (brue_pc_data_12    ),
.brue_op1_val       (brue_op1_val_12    ),
.brue_op2_val       (brue_op2_val_12    ),
.brue_imm_val       (brue_imm_val_12    ),
//.brue_rd_ind        (brue_rd_ind_12     ),
.brue_rd_vld        (brue_rd_vld_12     ),
.brue_bp_taddr      (brue_bp_taddr_12   ),
.brue_bp_taken      (brue_bp_taken_12   ),
.brue_bp_bhtv       (brue_bp_bhtv_12    ),
.brue_bp_phtv       (brue_bp_phtv_12    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_12        ),
.lsue_issue         (lsu_pick_vec_12    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_12),
.lsue_ctrl_load     (lsue_ctrl_load_12  ),
.lsue_ctrl_store    (lsue_ctrl_store_12 ),
.lsue_ctrl_word     (lsue_ctrl_word_12  ),
.lsue_ctrl_half     (lsue_ctrl_half_12  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_12  ),
.lsue_inst_id       (lsue_inst_id_12    ),
.lsue_op1_val       (lsue_op1_val_12    ),
.lsue_op2_val       (lsue_op2_val_12    ),
.lsue_store_data    (lsue_store_data_12 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_13(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_13       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_13      ),
.isqe_valid         (isqe_valid_13      ),
.isqe_ready         (isqe_ready_13      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_13        ),
.alue_issue         (alu_pick_vec_13        ),
.alue_ctrl_land     (alue_ctrl_land_13  ),
.alue_ctrl_lor      (alue_ctrl_lor_13   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_13  ),
.alue_ctrl_sll      (alue_ctrl_sll_13   ),
.alue_ctrl_srl      (alue_ctrl_srl_13   ),
.alue_ctrl_sra      (alue_ctrl_sra_13   ),
.alue_ctrl_add      (alue_ctrl_add_13   ),
.alue_ctrl_sub      (alue_ctrl_sub_13   ),
.alue_ctrl_slt      (alue_ctrl_slt_13   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_13),
.alue_inst_id       (alue_inst_id_13    ),
.alue_op1_val       (alue_op1_val_13    ),
.alue_op2_val       (alue_op2_val_13    ),
//.alue_rd_ind        (alue_rd_ind_13     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_13        ),
.brue_issue         (bru_pick_vec_13    ),
.brue_ctrl_beq      (brue_ctrl_beq_13   ),
.brue_ctrl_bne      (brue_ctrl_bne_13   ),
.brue_ctrl_blt      (brue_ctrl_blt_13   ),
.brue_ctrl_bge      (brue_ctrl_bge_13   ),
.brue_ctrl_jal      (brue_ctrl_jal_13   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_13  ),
.brue_inst_id       (brue_inst_id_13    ),
.brue_pc_data       (brue_pc_data_13    ),
.brue_op1_val       (brue_op1_val_13    ),
.brue_op2_val       (brue_op2_val_13    ),
.brue_imm_val       (brue_imm_val_13    ),
//.brue_rd_ind        (brue_rd_ind_13     ),
.brue_rd_vld        (brue_rd_vld_13     ),
.brue_bp_taddr      (brue_bp_taddr_13   ),
.brue_bp_taken      (brue_bp_taken_13   ),
.brue_bp_bhtv       (brue_bp_bhtv_13    ),
.brue_bp_phtv       (brue_bp_phtv_13    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_13        ),
.lsue_issue         (lsu_pick_vec_13    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_13),
.lsue_ctrl_load     (lsue_ctrl_load_13  ),
.lsue_ctrl_store    (lsue_ctrl_store_13 ),
.lsue_ctrl_word     (lsue_ctrl_word_13  ),
.lsue_ctrl_half     (lsue_ctrl_half_13  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_13  ),
.lsue_inst_id       (lsue_inst_id_13    ),
.lsue_op1_val       (lsue_op1_val_13    ),
.lsue_op2_val       (lsue_op2_val_13    ),
.lsue_store_data    (lsue_store_data_13 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_14(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_14       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_14      ),
.isqe_valid         (isqe_valid_14      ),
.isqe_ready         (isqe_ready_14      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_14        ),
.alue_issue         (alu_pick_vec_14        ),
.alue_ctrl_land     (alue_ctrl_land_14  ),
.alue_ctrl_lor      (alue_ctrl_lor_14   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_14  ),
.alue_ctrl_sll      (alue_ctrl_sll_14   ),
.alue_ctrl_srl      (alue_ctrl_srl_14   ),
.alue_ctrl_sra      (alue_ctrl_sra_14   ),
.alue_ctrl_add      (alue_ctrl_add_14   ),
.alue_ctrl_sub      (alue_ctrl_sub_14   ),
.alue_ctrl_slt      (alue_ctrl_slt_14   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_14),
.alue_inst_id       (alue_inst_id_14    ),
.alue_op1_val       (alue_op1_val_14    ),
.alue_op2_val       (alue_op2_val_14    ),
//.alue_rd_ind        (alue_rd_ind_14     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_14        ),
.brue_issue         (bru_pick_vec_14    ),
.brue_ctrl_beq      (brue_ctrl_beq_14   ),
.brue_ctrl_bne      (brue_ctrl_bne_14   ),
.brue_ctrl_blt      (brue_ctrl_blt_14   ),
.brue_ctrl_bge      (brue_ctrl_bge_14   ),
.brue_ctrl_jal      (brue_ctrl_jal_14   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_14  ),
.brue_inst_id       (brue_inst_id_14    ),
.brue_pc_data       (brue_pc_data_14    ),
.brue_op1_val       (brue_op1_val_14    ),
.brue_op2_val       (brue_op2_val_14    ),
.brue_imm_val       (brue_imm_val_14    ),
//.brue_rd_ind        (brue_rd_ind_14     ),
.brue_rd_vld        (brue_rd_vld_14     ),
.brue_bp_taddr      (brue_bp_taddr_14   ),
.brue_bp_taken      (brue_bp_taken_14   ),
.brue_bp_bhtv       (brue_bp_bhtv_14    ),
.brue_bp_phtv       (brue_bp_phtv_14    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_14        ),
.lsue_issue         (lsu_pick_vec_14    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_14),
.lsue_ctrl_load     (lsue_ctrl_load_14  ),
.lsue_ctrl_store    (lsue_ctrl_store_14 ),
.lsue_ctrl_word     (lsue_ctrl_word_14  ),
.lsue_ctrl_half     (lsue_ctrl_half_14  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_14  ),
.lsue_inst_id       (lsue_inst_id_14    ),
.lsue_op1_val       (lsue_op1_val_14    ),
.lsue_op2_val       (lsue_op2_val_14    ),
.lsue_store_data    (lsue_store_data_14 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  

frv_isq_entry _frv_isq_entry_15(                
.clk                (clk                ),
.rst_n              (rst_n              ),
.pd_rst             (pd_rst             ),
.isqe_wreq          (isqe_wreq_15       ),
.isq_inst_id        (isq_inst_id        ),
//.isqe_flush         (isqe_flush_15      ),
.isqe_valid         (isqe_valid_15      ),
.isqe_ready         (isqe_ready_15      ),
.isq_inst_data      (isq_inst_data      ),
.isq_exp_vld        (isq_exp_vld        ),
.isq_exp_code       (isq_exp_code       ),
.isq_pc_data        (isq_pc_data        ),
.isq_alu_vld        (isq_alu_vld        ),
.isq_alu_land       (isq_alu_land       ),
.isq_alu_lor        (isq_alu_lor        ),
.isq_alu_lxor       (isq_alu_lxor       ),
.isq_alu_sll        (isq_alu_sll        ),
.isq_alu_srl        (isq_alu_srl        ),
.isq_alu_sra        (isq_alu_sra        ),
.isq_alu_add        (isq_alu_add        ),
.isq_alu_sub        (isq_alu_sub        ),
.isq_alu_slt        (isq_alu_slt        ),
.isq_alu_unsign     (isq_alu_unsign     ),
.isq_bru_vld        (isq_bru_vld        ),
.isq_bru_beq        (isq_bru_beq        ),
.isq_bru_bne        (isq_bru_bne        ),
.isq_bru_blt        (isq_bru_blt        ),
.isq_bru_bge        (isq_bru_bge        ),
.isq_bru_jal        (isq_bru_jal        ),
.isq_bru_jalr       (isq_bru_jalr       ),
.isq_bp_taddr       (isq_bp_taddr       ),
.isq_bp_taken       (isq_bp_taken       ),
.isq_bp_bhtv        (isq_bp_bhtv        ),
.isq_bp_phtv        (isq_bp_phtv        ),
.isq_lsu_vld        (isq_lsu_vld        ),
.isq_lsu_unsign     (isq_lsu_unsign     ),
.isq_lsu_load       (isq_lsu_load       ),
.isq_lsu_store      (isq_lsu_store      ),
.isq_lsu_word       (isq_lsu_word       ),
.isq_lsu_half       (isq_lsu_half       ),
.isq_lsu_byte       (isq_lsu_byte       ),
.isq_csr_vld        (isq_csr_vld        ),
.isq_csr_write      (isq_csr_write      ),
.isq_csr_set        (isq_csr_set        ),
.isq_csr_clr        (isq_csr_clr        ),
.isq_rs1_vld        (isq_rs1_vld        ),
.isq_rs1_rdy        (reg_rs1_rdy        ),
.isq_rs1_ind        (isq_rs1_ind        ),
// .isq_rs1_type       (isq_rs1_type       ),
.isq_rs2_vld        (isq_rs2_vld        ),
.isq_rs2_rdy        (reg_rs2_rdy        ),
.isq_rs2_ind        (isq_rs2_ind        ),
//.isq_rs2_type       (isq_rs2_type       ),
.isq_rs1_val        (reg_rs1_val        ),
.isq_rs2_val        (reg_rs2_val        ),
.isq_imm_vld        (isq_imm_vld        ),
.isq_imm_data       (isq_imm_data       ),
.isq_rd_vld         (isq_rd_vld         ),
//.isq_rd_ind         (isq_rd_ind         ),
//.isq_rdm_ind        (isq_rdm_ind        ),
.isq_pc_used        (isq_pc_used        ),
.alue_req           (alue_req_15        ),
.alue_issue         (alu_pick_vec_15        ),
.alue_ctrl_land     (alue_ctrl_land_15  ),
.alue_ctrl_lor      (alue_ctrl_lor_15   ),
.alue_ctrl_lxor     (alue_ctrl_lxor_15  ),
.alue_ctrl_sll      (alue_ctrl_sll_15   ),
.alue_ctrl_srl      (alue_ctrl_srl_15   ),
.alue_ctrl_sra      (alue_ctrl_sra_15   ),
.alue_ctrl_add      (alue_ctrl_add_15   ),
.alue_ctrl_sub      (alue_ctrl_sub_15   ),
.alue_ctrl_slt      (alue_ctrl_slt_15   ),
.alue_ctrl_unsign   (alue_ctrl_unsign_15),
.alue_inst_id       (alue_inst_id_15    ),
.alue_op1_val       (alue_op1_val_15    ),
.alue_op2_val       (alue_op2_val_15    ),
//.alue_rd_ind        (alue_rd_ind_15     ),
.alu_fwd_vld        (alu_fwd_vld        ),
.alu_fwd_val        (alu_fwd_val        ),
.alu_fwd_inst_id     (alu_fwd_inst_id     ),
.brue_req           (brue_req_15        ),
.brue_issue         (bru_pick_vec_15    ),
.brue_ctrl_beq      (brue_ctrl_beq_15   ),
.brue_ctrl_bne      (brue_ctrl_bne_15   ),
.brue_ctrl_blt      (brue_ctrl_blt_15   ),
.brue_ctrl_bge      (brue_ctrl_bge_15   ),
.brue_ctrl_jal      (brue_ctrl_jal_15   ),
.brue_ctrl_jalr     (brue_ctrl_jalr_15  ),
.brue_inst_id       (brue_inst_id_15    ),
.brue_pc_data       (brue_pc_data_15    ),
.brue_op1_val       (brue_op1_val_15    ),
.brue_op2_val       (brue_op2_val_15    ),
.brue_imm_val       (brue_imm_val_15    ),
//.brue_rd_ind        (brue_rd_ind_15     ),
.brue_rd_vld        (brue_rd_vld_15     ),
.brue_bp_taddr      (brue_bp_taddr_15   ),
.brue_bp_taken      (brue_bp_taken_15   ),
.brue_bp_bhtv       (brue_bp_bhtv_15    ),
.brue_bp_phtv       (brue_bp_phtv_15    ),
.bru_fwd_vld        (bru_fwd_vld        ),
.bru_fwd_inst_id    (bru_fwd_inst_id    ),
.bru_fwd_rd_vld     (bru_fwd_rd_vld     ),
.bru_fwd_val        (bru_fwd_val        ),
.bru_flush          (bru_flush          ),
.lsue_req           (lsue_req_15        ),
.lsue_issue         (lsu_pick_vec_15    ),
.lsue_ctrl_unsign   (lsue_ctrl_unsign_15),
.lsue_ctrl_load     (lsue_ctrl_load_15  ),
.lsue_ctrl_store    (lsue_ctrl_store_15 ),
.lsue_ctrl_word     (lsue_ctrl_word_15  ),
.lsue_ctrl_half     (lsue_ctrl_half_15  ),
.lsue_ctrl_byte     (lsue_ctrl_byte_15  ),
.lsue_inst_id       (lsue_inst_id_15    ),
.lsue_op1_val       (lsue_op1_val_15    ),
.lsue_op2_val       (lsue_op2_val_15    ),
.lsue_store_data    (lsue_store_data_15 ),
.lsu_fwd_inst_id    (lsu_fwd_inst_id    ),
.lsu_fwd_vld        (lsu_fwd_vld        ),
.lsu_fwd_rd_vld     (lsu_fwd_rd_vld     ),
.lsu_fwd_val        (lsu_fwd_val        ) 
);  


wire [5:0] alu_out_inst_id;

assign alu_inst_id = alu_out_inst_id;

//DFFs
dffr #(1)                                 isq_ready_ff       (clk,rst_n,1'b1,isq_ready_nxt      ,isq_ready      );
dffr #(1)                                 alu_req_ff         (clk,rst_n,1'b1,alu_req_nxt        ,alu_req        );
dffr #(1)                                 alu_ctrl_land_ff   (clk,rst_n,1'b1,alu_ctrl_land_nxt  ,alu_ctrl_land  );
dffr #(1)                                 alu_ctrl_lor_ff    (clk,rst_n,1'b1,alu_ctrl_lor_nxt   ,alu_ctrl_lor   );
dffr #(1)                                 alu_ctrl_lxor_ff   (clk,rst_n,1'b1,alu_ctrl_lxor_nxt  ,alu_ctrl_lxor  );
dffr #(1)                                 alu_ctrl_sll_ff    (clk,rst_n,1'b1,alu_ctrl_sll_nxt   ,alu_ctrl_sll   );
dffr #(1)                                 alu_ctrl_srl_ff    (clk,rst_n,1'b1,alu_ctrl_srl_nxt   ,alu_ctrl_srl   );
dffr #(1)                                 alu_ctrl_sra_ff    (clk,rst_n,1'b1,alu_ctrl_sra_nxt   ,alu_ctrl_sra   );
dffr #(1)                                 alu_ctrl_add_ff    (clk,rst_n,1'b1,alu_ctrl_add_nxt   ,alu_ctrl_add   );
dffr #(1)                                 alu_ctrl_sub_ff    (clk,rst_n,1'b1,alu_ctrl_sub_nxt   ,alu_ctrl_sub   );
dffr #(1)                                 alu_ctrl_slt_ff    (clk,rst_n,1'b1,alu_ctrl_slt_nxt   ,alu_ctrl_slt   );
dffr #(1)                                 alu_ctrl_unsign_ff (clk,rst_n,1'b1,alu_ctrl_unsign_nxt,alu_ctrl_unsign);
dffr #(5+1)                   alu_inst_id_ff     (clk,rst_n,1'b1,alu_inst_id_nxt    ,alu_out_inst_id    ); 
dffr #(32)                                alu_op1_val_ff     (clk,rst_n,1'b1,alu_op1_val_nxt    ,alu_op1_val    );
dffr #(32)                                alu_op2_val_ff     (clk,rst_n,1'b1,alu_op2_val_nxt    ,alu_op2_val    );

dffr #(1)                                 bru_req_ff         (clk,rst_n,1'b1,bru_req_nxt        ,bru_req          );
dffr #(1)                                 bru_ctrl_beq_ff    (clk,rst_n,1'b1,bru_ctrl_beq_nxt   ,bru_ctrl_beq     );
dffr #(1)                                 bru_ctrl_bne_ff    (clk,rst_n,1'b1,bru_ctrl_bne_nxt   ,bru_ctrl_bne     );
dffr #(1)                                 bru_ctrl_blt_ff    (clk,rst_n,1'b1,bru_ctrl_blt_nxt   ,bru_ctrl_blt     );
dffr #(1)                                 bru_ctrl_bge_ff    (clk,rst_n,1'b1,bru_ctrl_bge_nxt   ,bru_ctrl_bge     );
dffr #(1)                                 bru_ctrl_jal_ff    (clk,rst_n,1'b1,bru_ctrl_jal_nxt   ,bru_ctrl_jal     );
dffr #(1)                                 bru_ctrl_jalr_ff   (clk,rst_n,1'b1,bru_ctrl_jalr_nxt  ,bru_ctrl_jalr    );
dffr #(5+1)                   bru_inst_id_ff     (clk,rst_n,1'b1,bru_inst_id_nxt    ,bru_inst_id      ); // Instruction ID  
dffr #(32)                                bru_pc_data_ff     (clk,rst_n,1'b1,bru_pc_data_nxt    ,bru_pc_data      );
dffr #(32)                                bru_op1_val_ff     (clk,rst_n,1'b1,bru_op1_val_nxt    ,bru_op1_val      );
dffr #(32)                                bru_op2_val_ff     (clk,rst_n,1'b1,bru_op2_val_nxt    ,bru_op2_val      );
dffr #(32)                                bru_imm_val_ff     (clk,rst_n,1'b1,bru_imm_val_nxt    ,bru_imm_val      );

dffr #(1)                                 bru_rd_vld_ff      (clk,rst_n,1'b1,bru_rd_vld_nxt     ,bru_rd_vld       );
dffr #(32)                                bru_bp_taddr_ff    (clk,rst_n,1'b1,bru_bp_taddr_nxt   ,bru_bp_taddr     ); // bp target addr
dffr #(1)                                 bru_bp_taken_ff    (clk,rst_n,1'b1,bru_bp_taken_nxt   ,bru_bp_taken     ); // bp taken
dffr #(4)                                 bru_bp_bhtv_ff     (clk,rst_n,1'b1,bru_bp_bhtv_nxt    ,bru_bp_bhtv      ); // BHT Entry Value
dffr #(32)                                bru_bp_phtv_ff     (clk,rst_n,1'b1,bru_bp_phtv_nxt    ,bru_bp_phtv      ); // PHT Entry Value  
dffr #(1)                                 lsu_req_ff         (clk,rst_n,1'b1,lsu_req_nxt        ,lsu_req          );
dffr #(1)                                 lsu_ctrl_unsign_ff (clk,rst_n,1'b1,lsu_ctrl_unsign_nxt,lsu_ctrl_unsign  );
dffr #(1)                                 lsu_ctrl_load_ff   (clk,rst_n,1'b1,lsu_ctrl_load_nxt  ,lsu_ctrl_load    );
dffr #(1)                                 lsu_ctrl_store_ff  (clk,rst_n,1'b1,lsu_ctrl_store_nxt ,lsu_ctrl_store   );
dffr #(1)                                 lsu_ctrl_word_ff   (clk,rst_n,1'b1,lsu_ctrl_word_nxt  ,lsu_ctrl_word    );
dffr #(1)                                 lsu_ctrl_half_ff   (clk,rst_n,1'b1,lsu_ctrl_half_nxt  ,lsu_ctrl_half    );
dffr #(1)                                 lsu_ctrl_byte_ff   (clk,rst_n,1'b1,lsu_ctrl_byte_nxt  ,lsu_ctrl_byte    );
dffr #(5+1)                   lsu_inst_id_ff     (clk,rst_n,1'b1,lsu_inst_id_nxt    ,lsu_inst_id      ); // Instruction ID  
dffr #(32)                                lsu_op1_val_ff     (clk,rst_n,1'b1,lsu_op1_val_nxt    ,lsu_op1_val      );
dffr #(32)                                lsu_op2_val_ff     (clk,rst_n,1'b1,lsu_op2_val_nxt    ,lsu_op2_val      );    
dffr #(32)                                lsu_store_data_ff  (clk,rst_n,1'b1,lsu_store_data_nxt ,lsu_store_data   );

endmodule

